Abstract: A voltage controlled oscillator (VCO) circuit having a cascoded output stage has been provided. The VCO circuit includes an oscillation stage which utilizes a negative resistance technique for oscillation, and an output stage that is coupled in cascode with the oscillation stage thereby minimizing the power dissipation and allowing the output resistance of the VCO circuit to be adjusted for maximum drive capability.

Abstract: A memory circuit which includes a memory SCR and an output SCR is provided. The memory SCR is coupled between the input terminal and the common terminal of the memory circuit wherein the input terminal is the control terminal of the output SCR and the output SCR is coupled across the output terminal and the common terminal of the memory circuit. When the memory SCR latches, it functions to subsequently latch the output SCR. Because the output SCR has a greater forward operating voltage than the memory SCR and by providing a current path from the output terminal to the memory SCR, the memory SCR remains latched during the transition period of when the output SCR goes from a latched state to an unlatched state.

Abstract: A circuit for generating precise, phase shifted, CMOS level output signals with respect to an input data signal has been provided. The circuit utilizes a phase-locked loop for generating a precise clock signal. This precise clock signal is then utilized to clock a plurality of serially-coupled flip-flops wherein two-times the input data signal is applied to the data input of the first serially-coupled flip-flop. The outputs of the serially-coupled flip-flops are ECL signals which are then translated to CMOS level signals via ECL-CMOS translators. Finally, the output signals of the translators are respectively used to clock divide-by-two configured flip-flops in order to provide the plurality of precise, phase shifted CMOS output signals. The plurality of precise, phase shifted, CMOS output signals have a 50% duty cycle and represent phase shifted versions of the input data signal wherein the minimum time delay between signals is substantially equal to the period of the precise clock signal.

Abstract: A LCD vertical scrolling mechanism automatically tracks addresses of information scrolled on a LCD. A counter is initialized to a value latched in a vector register when a frame signal is received. Subsequent BPCLK signals step the adder through a series of values. These values are relayed through two bus selectors to segment drivers for the LCD. One of the bus selectors is coupled to the counter in parallel with a subtracter. When a value from the counter exceeds a predetermined value equal to the MUX of the LCD, the subtracter takes the difference between the predetermined MUX value and the value received from the counter and directs the parallel bus selector to relay the difference to the RAM of a segment driver. An adder is coupled to the other bus selector and to the vector register. When the MCU needs to fetch information from the segment drivers, the MCU relays a LCD address where the information is displayed, to the adder.

Abstract: A driver for a stepper motor including means (Q45, 45, 47, 402) for sampling the current in a motor winding (43) at an instant determined by means (401, 400)for generating a predetermined delay following winding commutation. The sample is compared with winding current by a comparator (403) the output of which is stored at a subsequent instant in a flip-flop (416) to provide an output (42). Current generated within the windings due to rotor motion provide a difference in output when the motor is running or blocked. The invention provides a solution to the problem of motion detection of a stepper motor without recourse to a positional sensor.

Abstract: An on-chip self-test circuit has been provided that allows for accurately testing a device such as prescaler at high frequencies. The on-chip self-test circuit includes a voltage controlled oscillator for providing high frequency signals to the device under test.The on-chip self-test circuit is rendered active only when one desires to test the device. Thus, when not testing, the on-chip self-test circuit is transparent to the device and consumes substantially zero power.

Abstract: A circuit for producing a display indicative of a bicycle rider's pedaling technique. The circuit measures the time required for the pedals to move through a given angle of rotation. The circuit then calculates the relative pedal velocity over the angle of rotation. This process is repeated over an entire circle of rotation to determine the variations in pedal velocity as the pedal moves through a full circle. Since the pedal velocity is related to the pedaling force applied by the rider, the variations in pedaling force can be determined. Further, the circuit has a display unit which shows a rotating line of varying length to indicate the pedaling force applied as the pedals move respectively through a full circle.

Abstract: A logic circuit for testing the reliability of an ASIC includes an array circuit having a plurality of matrix arrays each having a plurality of inputs. The plurality of matrix arrays being positioned in a predetermined row and column of the array circuit and being responsive to a plurality of input signals applied thereto for providing a respective row and column output. A parity circuit responsive to the row and column outputs of the plurality of matrix arrays for causing an output signal at an output of the logic circuit to be in a first logic state whenever the row outputs of the plurality of matrix arrays are logically different, or whenever the column outputs of the plurality of matrix arrays are logically different. A stimulus circuit coupled to the plurality of inputs of the plurality of matrix arrays for supplying the plurality of input signals to exhaustively stimulate each one of the plurality of matrix arrays with all possible logic combinations.

Abstract: A charge pump circuit (10) has been provided for maintaining the currents sunk by each of the bottom current sources (12, 14) substantially equal to the current sourced from a first upper current source (16). The present invention maintains the voltage across a second upper current source (64) that determines the current for the lower current sources to be modified with respect to corresponding changes in the first upper current source wherein these changes in the first upper current source are due to a varying voltage occurring at the output (18) of the charge pump circuit.

Abstract: A single ended input comparator circuit having an input inverter stage and a voltage reference circuit is provided. The voltage reference circuit modulates the voltage appearing across the inverter stage thereby varying the switching threshold voltage level of the inverter stage and providing hysteresis for the comparator circuit. Further, by appropriately choosing the widths and lengths of the transistors used in the inverter stage and the voltage reference circuit, a zero temperature coefficient for the comparator circuit is achieved.

Abstract: A telephone line card circuit includes an operational amplifier circuit having first and second inputs and an output. A field-effect transistor circuit has first, second and control electrodes, the control electrode is coupled to the output of the operational amplifier circuit, the first electrode is coupled to the TIP/RING terminal, and the second electrode is coupled to the second input of the operational amplifier circuit. A first resistor is coupled between the TIP/RING terminal and the first input of the operational amplifier circuit. A second resistor is coupled between the first input of the operational amplifier circuit and a terminal of the circuit whereby the terminal of the circuit is typically coupled to a supply voltage terminal.

Abstract: A method for protecting a semiconductor power die has been provided. The method involves inserting an integrated circuit die between the gate lead of a package containing the semiconductor power die and the actual gate terminal of the semiconductor power die. As a result, any current flowing into the gate lead of the package must pass through the integrated circuit die before entering the semiconductor power die. This allows the integrated circuit die to monitor and control the semiconductor power die.

Abstract: A mute circuit for an audio amplifier has been provided. The mute circuit alternately switches from a normal mode of operation to a mute mode of operation. In the normal mode of operation, the mute circuit utilizes a first op amp circuit to amplify an input signal by a predetermined factor. In the mute mode of operation, the mute circuit utilizes a second op amp circuit which is configured as an unity gain amplifier. In the mute mode, DC shifts occurring at the output of the second op amp circuit are minimized. Further, the second op amp circuit has a low output impedance thereby providing excellent attenuation of an audio input signal when the mute circuit is utilized in an audio amplifier application.

Abstract: A r.f. wideband high power amplifier (1) receives an input signal at its input via a coupler (7) whenever a signal for amplification is applied to an input port (15). The output of the amplifier (1) is tapped by a coupler (8) and fed to an input of a comparator (3). The input signal applied at the input port (15) is fed to a second input of the comparator (3) via a delay line (5), arranged to introduce a delay substantially equal to that of the power amplifier (1). The comparator (3) produces at its output an error signal representative of the difference between the input signal fed via the amplified and the delayed path. A combiner (16) serves to introduce the amplified error signal to the amplifier output signal such that the error signal is in anti-phase therewith. Thus, the resultant signal produced at an output port (4) has had feed forward distortion cancellation.

Abstract: A block architected integrated circuit having predetermined power and signal grid structures is provided. The integrated circuit includes a plurality of function blocks such as firm function blocks, standard cell logic blocks, and gate array logic blocks which are all designed according to the power and signal grid structures of the integrated circuit and from standard library elements of the base cell array. These function blocks have full floating capability with respect to the granularity of the power and signal grid structures.The integrated circuit also includes one or more hard function blocks which are not designed according to the power or signal grid structures of the integrated circuit. Further, the integrated circuit may also include one or more blocks which are designed from a different technology than the base cell array of the integrated circuit and, thus are also not designed according to the power or signal grid structures of the integrated circuit.

Abstract: A comparator having programmable hysteresis is provided. The signal supplied to an inverting input of the comparator (18) is determined by the logic state of the output of comparator and is a programmable factor of one of two predetermined signals (V.sub.REF1 or V.sub.REF2). The programmable factor is determined by the logic states of a plurality of control signals and can be adjusted by varying the logic states of the plurality of control signals.

Abstract: In order to improve the distortion performance of a feed forward corrected amplifier, an amplifier arrangement includes a distortion generator (312) which is coupled between an input (15) and a main amplifier (1). The amplifier arrangement is such that the input signal passes to the distortion generator (312) via a coupler (307). The signal passes via a delay network (310) which compensates for the delay of the distortion generator (312) and is tapped by a coupler (308) to be combined by a coupler (313) with the distorted signal from the distortion generator (312). In this way the output of the distortion generator is subtracted from a sample of the input signal so that only the distortion remains to pass via phase (314) and amplitude (315) correction networks to be amplifier by a gain element (316) before being coupled back into the main signal path by a coupler (309). The correction is active over a portion of the main amplifier characteristics such as the compression region of the main amplifier.

Abstract: A fail safe level shifter assures that, when an input signal voltage level falls below a given threshold voltage, the output is either a constant high or no signal at all. Additionally, a range of digital high signals having a voltage less than the given threshold voltage may be shifted by the fail safe level shifter. The fail safe level shifter expands the width of an N-MOS channel of conventional level shifters by placing two MOS switches in parallel. The resultant resistance allows the fail safe level shifter to register those high signals which are below the given threshold voltage. One-half of the level shifter has a N-MOS channel about one-half the width of a N-MOS channel in the other half of the level shifter. Therefore, the narrower half is unable to fully activate given the low input signals received. The fail safe level shifter thus assures that the output will be a constant high.

Abstract: A memory sense amplifier with a latch circuit is provided. The combination of a sense amplifier and a latch circuit allows for increased speed operation and minimum space requirements on an integrated circuit. The memory sense amplifier receives complementary input logic signals that are typically from a memory cell and provides latched complementary output logic signals in response to the voltage levels of the complementary input logic signals.

Abstract: A circuit for trimming the input offset voltage of an input stage of an op amp includes variable resistors (20, 24) for providing variable voltages in series with the input voltage of the op amp. The voltage drop across the variable resistors is adjusted to compensate for any base-emitter voltage mismatches of the input transistors (12, 14) thereby making the input offset voltage of the op amp equal to zero. Further, the variable resistors can be replaced by resistive networks (40, 42) such that the resistive networks can be adjusted to provide an input stage with a zero temperature coefficient as well as a zero input offset voltage.