Abstract: An apparatus for filtering an input signal includes a first second order filter section having an output and an intermediate output, a second second order filter section having an input connected to the output of the first second order filter, and a gain stage coupling the output of the first second order filter section and the intermediate output of the first second order filter section to the output of the second second order filter section. The gain stage is coupled such that a transfer function between the output of the second second order filter section and the input of the second second order filter section is a biquadratic transfer function.

Abstract: A circuit that generates a write precompensation delay signal includes a precoder, a delayed clock pulse selector, a delayed clock pulse generator, and a non-return-to-zero (NRZ) modulator. A master clock signal and serialized data operating at the master clock rate are inputs to the precoder which generates a precoded data signal operating at the master clock rate. The delayed clock pulse selector generates clock pulse selection signals based on the precoded data. The delayed clock pulse generator generates at least two delayed clock signals, selects either none or one of the delayed clock signals according to the clock pulse selection signals, and generates a return-to-zero (RZ) signal whose time periods comprise either a zero if no delayed clock signal is selected or a pulse of the selected delayed clock signal. The NRZ modulator generates the precompensation signal from the RZ signal, and the precompensation signal has a maximum precompensation delay of at least 50% of the master clock time period.

Abstract: High-bandwidth, analog multiplexer circuits with low signal feed-through and good common mode properties are described. These are BiCMOS circuits with N-MOS control transistors which emphasize low parasitic capacitance through circuit layout techniques and the use of smaller geometry devices where possible. These circuits can be used in both single-ended and differential configurations and address applications having multiplexing ratio requirements ranging from 2-to-1 up to many-to-1.

Abstract: Magnetoresistive, MR, heads and giant magnetoresistive, GMR, heads are used in hard disk drive storage systems. The heads have a pinned layer whose magnetic orientation, if incorrect, gives rise to data read errors. A pinned layer reset method and circuit is provided to restore the magnetic orientation of the pinned layer by applying a reset pulse to the MR head. The circuit employs the existing low frequency cutoff capacitor in the initial amplification stage of the preamplifier to charge the magnitude of the reset pulse. The magnitude of the pulse is programmable by selecting bits in the existing write current digital to analog converter. The head select input transistor applies the pulse to the MR head. The pulse width is programmable as is the discharge rate. The settling value of the pulse is determined by the existing read current digital to analog converter value.

Abstract: An improved write drive circuit which provides an adjustable writer drive current and overshoot transient for a H-bridge drive circuit in a hard disk drive. The invention uses a variable capacitor circuit to give an initial boost to the write driver transistors. In a preferred embodiment, the capacitance of the variable capacitor is controlled by a word written to the disk drive pre-amp over the serial control port.

Abstract: To offer a technique that can form electrodes in a composite device without using a lift-off method. In the manufacture of a composite device 2 in which a wafer 50 that has a sacrificial layer 51 is used, a mask film 66 that has been patterned is formed; patterning is given to a structural layer 54, the sacrificial layer 51 is etched from the area that is exposed, a movable part 11 is formed in an area where said sacrificial layer 51 is removed, and a fixed part 10 is formed in an area where the sacrificial layer 51 remains; also, a thin metallic film 60 is formed and patterning is given before forming the mask film 66, with electrodes 37 for an external electrical connection being formed. A protective film thin titanium tungsten film 64 is formed on the surface of said thin metallic film 60, with the thin metallic film 60 being protected during etching of the sacrificial layer 51.

Abstract: A termination circuit to reduce the overshoot and undershoot that are generated when switching the voltage level of a transmission line. The terminating circuit (11) has a termination switching circuit (40) and an auxiliary switching circuit (41). When the voltage level of the termination (5) of the transmission line (4) is switched from a low level to a high level, the termination switching circuit (40) switches the termination (5) that is connected to the ground potential at a low level to the power supply voltage (Vcc) corresponding to a high level, but before that connection is completed, due to the fact that the auxiliary switching circuit (41) temporarily connects the termination (5) to the ground potential corresponding to a low level, the impedance of the terminating circuit (11) is temporarily lowered. Therefore, the overshoot and the undershoot that were generated in the past when switching the voltage level can be reduced.

Abstract: A step-up DC voltage converters circuit and method of operation which overcomes the problems associated with the prior art skip mode converters by reversing the flow of energy in the step-up DC voltage converter at the end of each switching cycle for a short constant time duration, thus making it possible to operate the step-up DC voltage converter over the full load current range at a fixed frequency which substantially facilitates filtering the output voltage. In addition to this the peak-to-peak output voltage ripple is less as compared to that of skip mode converters.

Abstract: A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a high-dielectric-constant material layer (e.g. undoped BST 36) overlaying the conductive lightly donor doped perovskite layer. The conductive lightly donor doped perovskite layer provides a substantially chemically and structurally stable electrical connection to the high-dielectric-constant material layer. A lightly donor doped perovskite generally has much less resistance than undoped, acceptor doped, or heavily donor doped HDC materials. The amount of donor doping to make the material conductive (or resistive) is normally dependent on the process conditions (e.g. temperature, atmosphere, grain size, film thickness and composition). This resistivity may be further decreased if the perovskite is exposed to reducing conditions.

Abstract: An interface circuit which can transmit signals at high speed in a back plane application, which, in turn, can transmit signals among multiple circuit substrates via the transmission lines on a back board. Card 52 of the present invention has input circuit 92, wiring 212, and clamping circuit 402. Wiring 212 is connected to the input of input circuit 92, and clamping circuit 402 is connected to wiring 212. A signal is transmitted from transmission line 3 on back board 2 to wiring 212 via socket 42. However, when the transmitted signal rises or drops significantly, the signal is clamped by clamping circuit 402 so that it will not go outside a certain voltage range. The vibration amplitude of the signal becomes small. Consequently, the time needed for the input potential of input circuit 92 to be stabilized can be reduced and signals can be transmitted at high speed.

Abstract: A driving circuit and a charging pump booster circuit capable of reducing the power consumption and the noise generated during switching. Transistors Q1 and Q2 are controlled based on a control signal input into an input terminal Tin, and a charge/discharge current is output to an output terminal Tout. The base of a transistor Q5, having almost the same characteristics as those of the transistor Q1, is connected to the base of the transistor Q1 in order to have the transistor Q5 generate a current corresponding to the turning on/off of the transistor Q1, and the current from said transistor Q5 is reflected toward a resistance element R1 by means of a current mirror circuit comprising transistors Q6 and Q7, so that base voltage of the transistor Q2 can be set lower while the transistor Q1 is on in order to hold the transistor Q2 to the OFF status. As a result, leak-through current in the transistors Q1 and Q2 can be reduced and switching noises created by said leak-through current can be reduced.

Abstract: The purpose of this invention is to ensure an active use of the inverse short-channel effect in the ratio circuit and to guarantee stable operation at low power source voltage. In this ratio circuit, N-channel MOS transistor 12 of CMOS circuit 10 on one side forms the drive element, while P-channel MOS transistor 18 of CMOS circuit 16 on the other side forms the load element. Said N-channel MOS transistor 12 on the drive side and P-channel MOS transistor 16 on the load side have their drain terminals electrically connected to each other through transfer gate 22 made of N-channel MOS transistor. MOS transistor 12 on the drive side has a single channel CHa with the inverse short-channel effect. MOS transistor 18 on the load side has plural, e.g., two, channels CHb1 and CHb2, connected in tandem, each of which displays the inverse short-channel effect.

Abstract: A grating (461) assisted coupling of a semiconductor waveguide to a dielectric waveguide (451) is provided with one or more reflective stacks (330, 332, 334) to enhance the coupling efficiency. The glass or dielectric core (458) may be efficiently butt-coupled to the core of an optical fiber (470). A laser and semiconductor waveguide, reflective stacks coupling grating, and dielectric waveguide are integrated on a single substrate. Further, multiple lasers (410, 420, 430, 440) with differing lasing frequencies may be integrated and their outputs grating coupled into a single dielectric waveguide (450) for wavelength division multiplexing.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g.

Abstract: According to one embodiment of the invention, a method of buffering instructions in a processor having a pipeline having a decode stage includes detecting stalling of the decode stage, reissuing a previous fetch for an instruction in a memory until the decode stage is no longer stalled, and writing the fetch instruction into an instruction buffer after the decode stage is no longer stalled.

Abstract: A semiconductor chip mounting method to prevent the occurrence of particles created while mounting the semiconductor chip onto a substrate using ultrasonic thermocompression bonding. The mounting method of the present invention utilizing ultrasonic vibrations involves the following steps: a semiconductor chip having conductive bumps on its main surface is held by its back via an elastic film using a suction tool having a suction hole, the semiconductor chip is positioned against a substrate provided with connection wires corresponding to said conductive bumps, and the semiconductor chip is mounted onto the substrate in such a manner that the conductive bumps connect to said connection wires, and ultrasonic vibrations are applied from the suction tool to the semiconductor chip via said film while said semiconductor chip is being pressed against said substrate in order to bond said conductive bumps with said connection wires.

Abstract: A voltage translator circuit for driving the rows or wordlines of Flash EEPROM memories, having control logic voltages in the range 0 to 3.3 volts, as well as operating voltages needed for reading, programming or erasing operations in the range −9 to 12 volts. The voltage translator circuit includes a first feedback transistor (TP4), the gate of which (node 18) is directly driven by the wordline, and a second feedback transistor (TN5), the gate of which is also driven by the wordline (node 18), inserted between the connection node (node 6) between the first feedback transistor (TP4) and the gate region of a first switch transistor (pull-up 3) and the input node (node 0) on the gate region of a second switch transistor (pull-down 2).

Abstract: A demodulator circuit for demodulating a signal ASK-modulated with modulation pulses equal in duration, and having a small depth of modulation and large dynamic range comprises an amplitude limiter (10) through which an amplitude-dependent current flows when the amplitude of the signal to be demodulated exceeds its limiting threshold value. Furthermore comprised is an envelope detector (12) to the input of which the signal to be demodulated is applied, as well as a differentiating network (14) configured so that it differentiates the output signal of the envelope detector (12) and outputs a signal pulse only when the change in amplitude of this output signal is in one direction. A bandpass filter (18) in the demodulator circuit passes, from a signal derived from an amplitude-dependent current from the amplitude limiter (10), the frequency component attributed to the duration of the modulation pulses.

Abstract: An MPEG video playback method and system that reduces delay at the time of video reproduction of an MPEG-compressed video signal. The invention discloses a video reproduction method in a video reproduction system containing an error-correction means, an MPEG decoding means, and buffers. In one embodiment, the signal held in the buffer is output as the video playback signal (block 6), and the output from the MPEG decoding means is output as a video playback signal (block 5). An embodiment of a method and system in which the buffer is arranged upstream to the MPEG decoding means is also disclosed.

Abstract: To offer a Reed-Solomon decoding device that can effectively prevent erroneous correction. A Reed-Solomon decoding method that conducts error correction and decodes by using erasure positions showing the position of units of errors for a Reed-Solomon encoded string having parity data of 2t (positive integer) units, which finds the number n for the unit of the error from the above-mentioned erasure position (S13), in the event 0 ≦m1≦n≦m2≦2t (m1, m2, and n are positive integers) (S14, S15, S18), finds the error value by conducting decoding calculations for the erasure error correction of n units (S19), and conducts the error operation by using the above-mentioned error value and the above-mentioned erasure position (S17).