Abstract: A system for controlling slew rate in a motor control circuit for a motor comprises a high side switching device coupled to a coil of the motor, the high side switching device operable to control a voltage excitation signal applied at the coil. The system also comprises a high side slew rate control circuit operable to control a slew rate of the voltage excitation signal. The high side slew rate control circuit includes: an amplifier having an output coupled to an input of the high side switching device, a current sink coupling a first input of the amplifier to ground, a capacitor further coupling the first input of the amplifier to ground, and a feedback path from an output of the high side switching device to a second input of the amplifier.

Abstract: In accordance with the present invention, an improved method and structure is provided for integrating polymer and other low dielectric constant materials, which may have undesirable properties, into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. Since the bond is typically weak between low-k materials such as polymers 18 and traditional dielectrics such as SiO.sub.2 22, the weak bonding may cause delamination or other problems during subsequent processing. The present invention increases yield and simplifies processing subsequent to application of the low-k material by providing an adhesion/protective layer 20 between the low-k material 18 and the intermetal dielectric 22. A preferred embodiment is a spun-on layer 20 of HSQ cured on a hotplate prior to application of the SiO.sub.2 intermetal dielectric.

Abstract: A voltage multiplier circuit or charge pump circuit for CMOS integrated circuits having high power efficiency, high current drive and efficient area utilization. An embodiment comprises two mirrored sections driven by control signals (PH00, PH01, PH0.sub.-- P; PH10, PH11, PH1.sub.-- P) generated by a logic circuitry which receives, as input signals, an enable signal (en) and a clock signal (clk), wherein each mirrored section includes N stages and each stage comprises a capacitor (C00, C01, C02; C10, C11, C12) having a lower terminal and an upper terminal, the lower terminal is connected to a first switch (INV0, NCH00, NCH01; INV1, NCH10, NCH11) that, in closed condition, couples the lower terminal of the capacitor to ground (GND), said lower terminal of the capacitor being additionally connected to a second switch (INV0, PCH00, PCH01; INV1, PCH10, PCH11) that, in closed condition, couples the lower terminal of the capacitor to the supply voltage (Vpp).

Abstract: The objective is to realize a semiconductor memory capable of avoiding an increase in the load of the sense amplifiers, easily realizing a large capacity and high integration of the memory, reducing the current consumption by the bit lines, and improving the access speed. Because the levels of the selection signal lines SHUS1, SHUE1, SHDS1, and SHDE1 are set by the control circuit, only one of the aforementioned four selection signal lines is selected at the time of memory access, other selection signal lines are held in unselect status, and the sense amplifiers in the sense amplifier bank SB1a and prescribed bit line pairs or extended bit line pairs are connected to each other by response in order to carry out read or write; thus, the load of the sense amplifiers can be reduced, and high speed, large capacity, and high integration can be achieved.

Abstract: Highly efficient, enhanced RLL and MTR constrained or modulation codes and a unified methodology for generating the same. The new codes also include partial error detection (PED) capability. RLL/PED code rates of 8/9, 16/17, 24/25 and 32/33 or higher are disclosed. The new generalized RLL/PED block coding schemes are derived with fixed length n: n/(n+1)(d=0, k=n-1/l=n), n/n+1(0,[n/2]/l=n+4) and m/(n+1)(d=0, k=[n/2]/l=n) for n.gtoreq.5 (where [ ]denotes the enteger part of the argument). The codes n/(n+1)(0,[n/2]/l=n+4) are also shown in a concatenated ECC/modulation architecture, where the modulation decoder, capable of detecting bits in error, generates symbol byte erasures to boost the performance of the outer ECC decoder.

Abstract: An improved structure for a thin multilayer capacitor where the electrodes are formed only on a portion of the ends of the package to reduce the footprint on the circuit board and the amount of noble metal used for each unit. The improved structure results from a manufacturing method that has additional advantages of reduced fabrication costs and fewer manufacturing steps.

Abstract: A field memory having a distributed architecture is disclosed and in particular a memory arranged in block, wherein each block stores a bit or bits of said word, said bits having a predetermined position within said word. The distributed architecture improves the transfer of data between the input/output buffers and the internal registers of the memory. A data cache and an improved input erasable realisation are also disclosed.

Abstract: A decoding scheme for a dual string DAC which reduces the size of the decoding logic while also reducing the number of switches between the two strings of resistors and also eliminating the need for Op-amps between the coarse and fine resistor strings. The present invention provides a decoding circuit to select adjacent pairs of taps 24 of the coarse resistor string 12 using simple decoding blocks 36. In one embodiment of the present invention, a 14 bit decoder is constructed with a course decoding logic of four 3-bit decoders, two levels of switches, an add-one circuit, a multiplexer, and a small amount of overflow logic. An advantage of the present invention is reduced area and power needed to implement the decoding logic for a decoder having only two levels of switches between the coarse and fine resistor strings.

Abstract: A circuit for reducing a potential difference between terminals of an open switch. A current source is arranged to supply charges to a capacitor through first and second switches. Charge is being supplied to the capacitor only when the first switch is closed. The current source and the capacitor are maintained at first and second reference potentials, respectively. The circuit further includes a voltage follower which has its output connected to the second switch and one of its inputs connected to the capacitor and the other input connected to its output. The output of the voltage follower is at the same potential as one terminal of the first switch so that when the second switch is closed, the two terminals of the first switch are at the same potentials as each other.

Abstract: A waveform shaping circuit free of error in the hold capacitor due to parasitic capacitance of the MOSFET transistor.

Abstract: A manufacturing method for semiconductor devices such as dynamic RAM, etc. which removes the layer part more on the high position than an arbitrary position on a step forming a gradation by just a prescribed thickness when flattening a layer with a gradation formed of a high position part and a low position part. Then the projecting part created after the etching existing more on the low position side than at the arbitrary position of the gradation is eliminated by heat treatment.

Abstract: This is a system and method of describing 3-D objects from single aerial images using shadows. The method may include using object shadow information to extract generalized cone description (sweep rule, cross-section and axis). Additionally, this generalized cone information may then be used to reconstruct a 3-D object. The method may model curved 3-D objects, such as curved buildings, cooling towers, chimneys and oil tanks in aerial images, as generalized cones.

Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Abstract: A low capacitance interconnect structure and process is provided for integrating low-k decomposed polymers into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines, for reduced capacitance over prior art structures. Embodiments of the present invention use polymers which typically decompose into gases with lower dielectric coefficients than the original polymer to provide a lower dielectric constant material between conductive interconnects on an integrated circuit. The materials are decomposed after being sealed in with a cap layer to prevent contamination of the gas filled void left after decomposition. The present invention also combines the advantages of SiO.sub.2 with low dielectric decomposed polymers by placing the low decomposed material only between tightly spaced lines. The low-k polymer material can be applied by spin-on techniques or by vapor deposition.

Abstract: Methods and processes to reduce the cost and cycle time of designing manufacturing flows are described, particularly for microelectronic integrated circuit processes. One embodiment of the present invention is a method which divides the task of designing process flows into a number of abstraction levels and provides mechanisms to translate between these levels of abstraction. The process is divided into a number of modules each having process constraints. Process constraints are propagated backwards from the final module to the first module, and may also be propagated forward from earlier modules to later modules of needed. This approach results in a top-down design methodology where requirements from higher levels of abstraction are successively reduced to lower abstraction levels, while meeting the constraints imposed by the lower levels.

Abstract: A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or deceased thermal dissipation. In a preferred embodiment, the gate capacitance is reduced over prior art methods and structures by etching to the gate 14 and directly contacting the p+ gate with a p-ohmic contact 24. In another embodiment, the area under the gate contact 22 is implanted with a "trim" dopant, where the trim dopant acts to reduce the doping of the drainlayer thereby reducing the capacitance. In another embodiment, the area under the exposed gate contact 22 is isolated by ion damaged to reduce the doping/conductivity of the n- drain layer below a portion of the gate layer to reduce the gate-to-drain capacitance.

Abstract: An address decoder with low power consumption of feedthrough current, leakage current, etc. Address bits AY0.sub.0 -AY0.sub.7 are respectively supplied to n-type gate terminals of CMOS transfer gates C.sub.0 -C.sub.7 and the gate terminals of PMOS transistors P.sub.0 -P.sub.7. Inverted address bits AY0.sub.0- -AY0.sub.7- are supplied to p-type gate terminals of the CMOS transfer gates C.sub.0 -C.sub.7. Enable signals AY3.sub.p, AY6.sub.q are respectively input to both input terminals of a NAND circuit 10. The output terminals of NAND circuit 10 are connected to the input terminals of CMOS transfer gates C.sub.0 -C.sub.7. The output terminals of CMOS transfer gates C.sub.0 -C.sub.7 are connected to the input terminals of the drivers D.sub.0 -D.sub.7 and the drain terminals of the PMOS transistors P.sub.0 -P.sub.7 via a node F.sub.0 -F.sub.7. The source terminals of PMOS transistors P.sub.0 -P.sub.7 are connected to a power supply voltage V.sub.cc, for example of 3.3 V. The output terminals of drivers D.sub.

Abstract: A clock generator contains a reference oscillator (10), a digital closed delay chain (12), a digital frequency divider (14) and a digital phase comparator (16). The frequency divider (14) is connected between the output of the adjustable delay chain (12) and one input of the phase comparator (16). The output of the reference oscillator (10) is connected to a further input of the phase comparator (16). Between the output of the phase comparator (16) and the delay chain (12) a digital up-down counter (18) is connected, the counting direction of which is determined by the output signal of the phase comparator (16) and by means of which the corresponding length of the delay chain (12) is adjustable.

Abstract: A full adder that operates rapidly with low power supply voltage and minimal power consumption, and further, that occupies a small area on a semiconductor element. A sum signal calculation circuit 10 of full adder 1 performs addition of input signals A and B and carry in signal C and outputs sum signal S.sub.out. Carry signal calculation circuit 16 outputs carry out signal C.sub.out corresponding to the combination of the logic values of input signals A and B and carry in signal C. Sum signal calculation circuit (10) is composed of addition signal generation circuit (12) and sum signal generation circuit (14). Addition signal generation circuit 12 performs XOR logic operations on input signals A and B. Sum signal generation circuit 14 outputs the results of full addition operations on inputs signals A and B and carry in signal C as sum signal S.sub.out, based on the results of XOR logic operations by addition signal generation circuit (12) and carry in signal C.

Abstract: A compressible keyboard utilizing flexible key skirts is disclosed to provide portable electronic devices, such as notebook computers with the capability of a full-size or nearly full-size keyboard allowing greater flexibility and easier input for the user without compromising the format. In specific embodiments, the present invention provides laptops, notebooks and sub-notebooks with increased size keyboards which approximate the size of a typical desktop computer keyboard when in use, but when in a non-use configuration smaller dimensions conforming to conventional form factors for these devices.