Abstract: A thermal detection system (10) includes a focal plane array (12), a thermal isolation structure (14), and an integrated circuit substrate (16). Focal plane array (12) includes thermal sensors (28), each having an associated thermal sensitive element (30). Thermal sensitive element (30) is coupled with one side to infrared absorber and common electrode assembly (36) and on the opposite side to an associated contact pad (20) disposed on the integrated circuit substrate (16). Reticulation kerfs (52a, 52b) separate adjacent thermal sensitive elements (30a, 30b, 30c) by a distance at least half the average width (44, 46) of a single thermal sensitive element (30a, 30b, 30c). A continuous, non-reticulated optical coating (38) may be disposed over thermal sensitive elements (30a, 30b, 30c) to maximize absorption of thermal radiation incident to focal plane array (12).

Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to form a top surface with rounded corners on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g. TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.

Abstract: Generally, the present invention utilizes dry plasma etching techniques such as Electron Cyclotron Resonance (ECR) to produce sloped sidewalls on a DRAM storage cell. The rounded corners of the lower electrode made by this technique allow the advanced dielectric material to be deposited without substantial cracking, and it also allows the capacitance to be closely predicted and controlled due to the uniformity in which the advanced dielectric layer can be fabricated. One embodiment of the present invention is method of making a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises a barrier layer (e.g. TiN 36), and an unreactive layer (e.g. Pt 42).

Abstract: A thermal isolation structure (10) is disposed between a focal plane array and an integrated circuit substrate (12). The thermal isolation structure (10) includes a mesa-type formation (16) and a mesa strip conductor (18, 26) extending from the top of the mesa-type formation (16) to an associated contact pad (14) on the integrated circuit substrate (12). After formation of the mesa-type formation (16) and the mesa strip conductor (18, 26), an anisotropic etch using the mesa strip conductor (18, 26) as an etch mask removes excess mesa material to form trimmed mesa-type formation (24) for improved thermal isolation. Bump bonding material (20) may be deposited on mesa strip conductor (18, 26) and can also be used as an etch mask during the anisotropic etch. Thermal isolation structure (100) can include mesa-type formations (102), each with a centrally located via (110) extending vertically to an associated contact pad (104) of integrated circuit substrate (106).

Abstract: An improved inductor/antenna (100)improves the selectivity of a recognition system (10) by ensuring that only the transponder (14) closest to the inductor/antenna (100) of an interrogator (12) receives therefrom, and reacts to, an interrogation signal (S1). The improved inductor/antenna (100) also receives the resulting recognition signal (S2) from the transponder (14) for analysis by the interrogator (12). The inductor/antenna (100) includes two or more coils (102, 104; 124, 126, 128, 130; 132, 134) which may be wound on ferromagnetic cores (108), spaced around a metal mass (46, 48) such as a lock cylinder (46) of an ignition switch (24). The shape, number, location and relative winding sense of the coils are selected to shape and locate the energy field (F; 118, 122) radiated by the inductor/antenna (100) so that only the transponder (14) in a key (26) which is inserted into or operating the ignition switch (24) responds to the interrogation signal (S1) radiated by the inductor/antenna (100).

Abstract: An improved method of forming a capacitor electrode for a microelectronic structure such as a dynamic read only memory is disclosed which has a high dielectric constant (HDC) material as a capacitor dielectric. According to an embodiment of the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material.

Abstract: An integrated vehicle communications system for on-board use within a vehicle which may also communicate with external portions of the system which includes miniaturized, self-contained read/write transponders 20, 22, 30 of the type disclosed in Schuermann U.S. Pat. No. 5,053,774, for providing functions within the vehicle, e.g., for sensing conditions and parameters, The on-board interrogation unit 10 interrogates and receives signals by RF communication provided by on-board antennas 14, 26, 28 between the interrogation unit and respective transponders for read/write responder operation. The processor 33 with display device 34a and/or control circuits 34b carries out on-board functions in response to such interrogation.

Abstract: A preferred embodiment of this invention is a silicon-on-insulator structure comprising a semiconductor substrate (e.g. Si 36), a buried insulator layer (e.g. SiO.sub.2 34) overlaying the substrate, wherein the buried layer is buried at two or more predetermined depths, and a surface silicon layer (e.g Si 32) overlaying the buried insulator, wherein the surface silicon layer has two or more predetermined thicknesses. Generally, by patterning and etching a screening material (e.g. SiO.sub.2 30) prior to ion implantation, preselected areas of the substrate with less or no screen material are formed with a thicker surface silicon layer, while other areas with more screen material are formed with a thinner surface silicon layer. The areas of different surface silicon thickness can be used to implement devices with different characteristics based on those thicknesses, within the same integrated circuit.

Abstract: Generally, the present invention is an optical waveguide circuit comprising a substrate 30, a non-organic waveguide channel 34 disposed within one or more cladding layers 32, 36 upon the substrate and an active cladding region comprising electro-optic 40, 43 or optically non-linear polymer material 46 adjacent to the waveguide channel wherein the phase of an optical signal within the waveguide channel may be modulated by controlling the index of refraction of the active cladding region. An embodiment of the present invention uses an inorganic optical waveguide 34 with a region of active organic cladding to provide a phase modulator for a Mach-Zender interferometer which can be used to implement high speed low loss switching of optical signals.

Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to form a top surface with rounded corners on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.

Abstract: A ferroelectric integrated circuit is provided in which a first layer of conducting lines (14) is formed over an insulating base layer (10). A first ferroelectric layer (16) is formed overlying the first layer of conducting lines (14). A second layer of conducting lines (18) is formed overlying the first ferroelectric layer (16) with each of the conducting lines of the second layer of conducting lines (18) being substantially perpendicular to the conducting lines of the first layer of conducting lines (14). Potentials placed on selected conducting lines in the first and second layers of conducting lines (14 and 18) polarize areas of the first ferroelectric layer (16) between intersections of the selected conducting lines. Multiple layers may be stacked to form a three-dimensional ferroelectric integrated circuit.

Abstract: A thermal isolation structure (10) is disposed between a focal plane array and an integrated circuit substrate (12). The thermal isolation structure (10) includes a mesa-type formation (16) and a mesa strip conductor (18, 26) extending from the top of the mesa-type formation (16) to an associated contact pad (14) on the integrated circuit substrate (12). After formation of the mesa-type formation (16) and the mesa strip conductor (18, 26), an anisotropic etch using the mesa strip conductor (18, 26) as an etch mask removes excess mesa material to form trimmed mesa-type formation (24) for improved thermal isolation. Bump bonding material (20) may be deposited on mesa strip conductor (18, 26) and can also be used as an etch mask during the anisotropic etch. Thermal isolation structure (100) can include mesa-type formations (102), each with a centrally located via (110) extending vertically to an associated contact pad (104) of integrated circuit substrate (106).

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelectric oxide) on the germanium layer. Preferably, the germanium layer is epitaxially grown on the semiconductor substrate. This is also a semiconductor structure, comprising: a semiconductor substrate; a germanium layer on the semiconductor substrate; and a high-dielectric constant oxide on the germanium layer. Preferably the germanium layer is single-crystal. Preferably the substrate is silicon and the germanium layer is less than about 1 nm thick or the substrate is gallium arsenide (in which case the thickness of the germanium layer is not as important). A second germanium layer 40 may be grown on top of the high-dielectric constant oxide and a conducting layer 42 (possibly epitaxial) grown on the second germanium layer.

Abstract: A preferred embodiment of this invention comprises a first thin dielectric buffer layer of a first leakage-current-density material (e.g. strontium titanate 32) with a first moderate-dielectric-constant, a high-dielectric-constant layer of a second leakage-current-density material (e.g. barium strontium titanate 34) overlaying the first thin dielectric buffer layer, and a second thin dielectric buffer layer of a third leakage-current-density material (e.g. strontium titanate 36) with a second moderate-dielectric-constant overlaying the high-dielectric-constant layer, wherein the first and third leakage-current-density materials have substantially lower leakage-current-densities than the second leakage-current-density material. The first and second thin moderate-dielectric-constant buffer layers (e.g. strontium titanate 32, 36) substantially limit the leakage-current-density of the structure, with only modest degradation of the dielectric constant of the structure.

Abstract: An improved inductor/antenna (100)improves the selectivity of a recognition system (10) by ensuring that only the transponder (14) closest to the inductor/antenna (100) of an interrogator (12) receives therefrom, and reacts to, an interrogation signal (S1). The improved inductor/antenna (100) also receives the resulting recognition signal (S2) from the transponder (14)for analysis by the interrogator (12). The inductor/antenna (100) includes two or more coils (102,104; 124,126,128,130; 132,134) which may be wound on ferromagnetic cores (108), spaced around a metal mass (46,48) such as a lock cylinder (46) of an ignition switch (24). The shape, number, location and relative winding sense of the coils are selected to shape and locate the energy field (F; 118,122) radiated by the inductor/antenna (100) so that only the transponder (14) in a key (26) which is inserted into or operating the ignition switch (24) responds to the interrogation signal (S1) radiated by the inductor/antenna (100).

Abstract: A system and method for testing the properties of semiconductor material including an enclosed chamber, a sample of semiconductor material under test having a polished surface portion and insulator layer over the polished surface portion supported in the chamber, a spring probe disposed within the chamber impinging against the insulator layer, a contact disposed on a surface portion of the semiconductor material under test, a pair of contacts disposed external to the chamber, each of the pair of contacts coupled to a different one of the contact and the spring probe and a container supporting the chamber and containing a cryogenic material therein surrounding the chamber. The semiconductor material is preferably a group II-VI composition, preferably HgCdTe. The contact disposed on the surface portion of the semiconductor material is preferably indium. A support, preferably sapphire, is provided for the sample.

Abstract: A thermal detection system (10) includes a focal plane array (12), a thermal isolation structure (14), and an integrated circuit substrate (16). Focal plane array (12) includes thermal sensors (28), each having an associated thermal sensitive element (30). Thermal sensitive element (30) is coupled with one side to infrared absorber and common electrode assembly (36) and on the opposite side to an associated contact pad (20) disposed on the integrated circuit substrate (16). Reticulation kerfs (52a, 52b) separate adjacent thermal sensitive elements (30a, 30b, 30c) by a distance at least half the average width (44, 46) of a single thermal sensitive element (30a, 30b, 30c). A continuous, non-reticulated optical coating (38) may be disposed over thermal sensitive elements (30a, 30b, 30c) to maximize absorption of thermal radiation incident to focal plane array (12).