Abstract: An array of raised lands disposed in columns and rows formed of ceramic material, particularly barium strontium titanate, is formed by making a die of resist material having a negative image pattern of the array on a ceramic substrate and then forming a slurry having a high solid content of the ceramic material, filling the pattern with the slurry and firing the filled die to produce a sintered array of pixels. In a modified embodiment a pressing pad 18 of deformable ceramic tape is formed and pressed into the die after the die has been filled with slurry 16 in order to compact the material and wipe the ceramic material from the sidewalls 12. In another embodiment a ceramic tape of the type used for the pressing pad is pressed into the die and after a short time removed from the die with the pixel array formed in the tape which is then fired to sinter the array.

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick.

Abstract: A metal interconnect fabrication process for hybrid solid state systems such as thermal imaging system (50). A plurality of vias (62) are formed in a focal plane array (60) between the thermal sensors (20) to expose a corresponding array of contact pads (84) on a silicon processor (80) bonded to the focal plane array (60). A metal film layer (30) is disposed on the focal plane array (60) to fill the vias (62). Photoresist material (32) is patterned on the metal layer (30) to correspond with the desired sensor signal flow path. With the photoresist material (32) still in place, the metal layer (30) is dry etched to produce the desired metal interconnect pattern by removing portions of the metal layer (30) unprotected by the photoresist material (32).

Abstract: An apparatus (10) and method are provided for directly viewing, through a viewport assembly (26), the process for forming a layer of mercury cadmium telluride of a predetermined composition on a surface of a wafer (not shown). According to the invention, a molten melt (20) comprising mercury, cadmium and tellurium is provided in a vertically oriented crystal growth chamber (14), which, in turn, is housed in a reactor tube (12). A wafer (not shown) is contacted with the crystal growth melt while cooling the melt below its liquidus temperature at a predetermined rate sufficient to cause a crystal growth layer of mercury cadmium telluride to form on the wafer (not shown). Viewports (26, 48) located approximately radially adjacent to the melt (22) provide direct see through capability to visually monitor the crystal growth process.

Abstract: A ferroelectric integrated circuit is provided in which a first layer of conducting lines (14) is formed over an insulating base layer (10). A first ferroelectric layer (16) is formed overlying the first layer of conducting lines (14). A second layer of conducting lines (18) is formed overlying the first ferroelectric layer (16) with each of the conducting lines of the second layer of conducting lines (18) being substantially perpendicular to the conducting lines of the first layer of conducting lines (14). Potentials placed on selected conducting lines in the first and second layers of conducting lines (14 and 18) polarize areas of the first ferroelectric layer (16) between intersections of the selected conducting lines. Multiple layers may be stacked to form a three-dimensional ferroelectric integrated circuit.

Abstract: A bonding apparatus (40) is provided for use in coupling a first substrate (20) with flip chip type interconnections (24) to a second substrate (22) having matching flip chip type interconnections (26). The bonding apparatus (40) includes a pedestal assembly (50) which may be used to align and couple the first substrate (20) with the second substrate (22) and transport the substrates (20 and 22) from the bonding apparatus (40) to a heater assembly (110). Magnetic force is used to maintain the alignment of the first substrate (20) with the second substrate (22) during temperature cycling within the heater assembly. The pedestal assembly (50) includes a magnet slidably disposed on the exterior of the pedestal assembly (50). For some applications, the magnet (60) may be formed from one or more permanent magnets. For other applications, magnet (60) may be formed from one or more electromagnets.

Abstract: An inverted thin film resistor structure comprises a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads (e.g. Al 36) overlaying a supporting layer (e.g. SiO.sub.2 32), an interlevel dielectric layer (e.g. SiO.sub.2 40) overlaying the supporting layer, and planarized so as to expose a top contact portion of the metallic interconnect leads, and an inverted thin film resistor (e.g. TaN 44) overlaying a portion of the planarized interlevel dielectric layer and overlaying the exposed top contact portion of the metallic interconnect leads. The novel inverted thin film resistor structure does not require a protective metal layer and does not require any vias in direct contact with the resistor. In addition, both the thin film resistor and the metallic interconnect can be formed with pattern and etch techniques.

Abstract: A preferred embodiment of this invention is a silicon-on-insulator structure comprising a semiconductor substrate (e.g. Si 36), a buried insulator layer (e.g. SiO.sub.2 34) overlaying the substrate, wherein the buried layer is buried at two or more predetermined depths, and a surface silicon layer (e.g. Si 32) overlaying the buried insulator, wherein the surface silicon layer has two or more predetermined thicknesses. Generally, by patterning and etching a screening material (e.g. SiO.sub.2 30) prior to ion implantation, preselected areas of the substrate with less or no screen material are formed with a thicker surface silicon layer, while other areas with more screen material are formed with a thinner surface silicon layer. The areas of different surface silicon thickness can be used to implement devices with different characteristics based on those thicknesses, within the same integrated circuit.

Abstract: A silicon on insulator integrated circuit device is provided which comprises a substrate (10), a buried oxide layer (12), and an outer silicon layer (14). A buried p-layer (16) and a buried n-well region (26) are formed in order to position p-n junctions beneath n-channel and p-channel devices respectively formed in the outer silicon layer (14) outwardly from the p-layer (16) and (n)-well (26).

Abstract: A bonding apparatus (40) having one or more electromagnets (60) is provided for use in coupling a first substrate (20) with flip chip type interconnections (24) to a second substrate (22) having matching flip chip type interconnections (26). The bonding apparatus (40) includes a pedestal assembly (50) which may be used to align and couple the first substrate (20) with the second substrate (22). The bonding apparatus (40) includes an electrical control system (108) with a control unit (130) for varying the amount of electrical power supplied to the electromagnet (60). One or more heater assemblies (110) are provided for temperature cycling of the substrates (20 and 22) during the bonding process. Magnetic force is used to maintain the alignment of the first substrate (20) with the second substrate (22) during temperature cycling.

Abstract: In accordance with the present invention, there is provided a method and structure which substantially reduce the leakage current between the surface layer and the substrate silicon that can be caused by the leakage pipes formed in the buried layer in a SIMOX process. A novel solution to this problem is to etch the silicon in these pipes by using an anodizing process. A preferred embodiment of this invention comprises the steps of exposing the surface layer (e.g. silicon 34) to an electrolytic solution (e.g dilute HF acid 38), and creating a potential difference between the substrate (e.g. silicon 30) and the solution, thereby causing current to flow through the leakage pipes (e.g. silicon 36) in the buried insulator layer (e.g. SiO.sub.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g.