Abstract: A direct current (DC) power supply supplies at least a first output and a second output having opposite voltage polarities. A protection circuit is coupled to the first and second outputs of the DC power supply, where the protection circuit includes a summing circuit that sums the voltages of the first and second outputs, an over-voltage detection circuit coupled to the summing circuit, and a shutdown latch. In the event of an overload or short circuit fault on one of the outputs of the power supply, the sum of the voltages of the first and second outputs exceeds a threshold voltage, causing the over-voltage detection circuit to output an over-voltage signal. In response to the over-voltage signal, the shutdown latch disables are at least one output of the DC power supply in order to prevent damage to its internal components.

Abstract: A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the bus which performs bus transactions utilizing n-byte packets of data. An adaptor is electrically coupled between the first processor and the bus which converts n-byte packets of data input from the bus to m-byte packets of data, and converts m-byte packets of data input from the first processor to n-byte packets of data, thereby enabling the first processor to transmit data to and receive data from the bus utilizing m-byte packets of data. In a second aspect of the present invention, a method and system are provided for arbitrating between two bus masters having disparate bus acquisition protocols. In response to a second bus master asserting a bus request when a first bus master controls the bus, control of the bus is removed from the first bus master.

Abstract: An apparatus is disclosed which supports memory updates within a data processing system including a number of processors. The apparatus includes a memory hierarchy including one or more upper levels of memory. Each upper level within the memory hierarchy includes one or more memory units which each store a subset of all data stored within an associated memory unit at a lower level of the memory hierarchy. Each memory unit at the highest level within the memory hierarchy is associated with a selected processor. In addition, the apparatus includes a reservation indicator associated with each memory unit within the memory hierarchy. For memory units at the highest level within the memory hierarchy, the reservation indicator specifies an address for which the processor associated with that memory unit holds a reservation. At each lower level within the memory hierarchy, the reservation indicator specifies addresses for which associated memory units at higher levels within the memory hierarchy hold a reservation.

Abstract: A computer system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect, where each such request transaction specifies an associated datum. The node controller of the second processing node handles each speculatively transmitted request transaction received in response to a directory state of its associated datum.

Abstract: A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processing node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node.

Abstract: A method and system for managing a cache including a plurality of entries are described. According to the method, first and second cache operation requests are received. In response to receipt of the second cache operation request, an entry among the plurality of entries is identified for replacement. In response to a conflict between the first and second cache operation requests arising because the first cache operation request specifies an entry among the plurality of entries including the entry identified for replacement, an entry among the plurality of entries other than the identified entry is replaced.

Abstract: A display window is displayed in association with at least one scroll bar at a terminal associated with a first user. Along the shaft of one ore more scroll bars, a distinctive visual location cue, such as a line in a color associated with a second user, is displayed to indicate the relative location within the shared data collection of the current and historical activity of a second user. A user may temporarily prohibit manipulation of a region within the shared data collection by other users by establishing a "lock" on the region. A lock region may comprise several lines of text, a portion of a graphical object, or other data within the shared data collection. To indicate the location of lock regions, lock region location cues are also displayed along the scroll bar.

Abstract: A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.

Abstract: A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that determines less than, greater than, and equal to condition code bits associated with the instruction concurrently with execution of the instruction by the execution unit. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits.

Abstract: A method and system for managing a cache including a plurality of entries are described. According to the method, first and second cache operation requests are received at the cache. In response to receipt of the first cache operation request, which specifies a particular entry among the plurality of entries, a single access of a coherency state associated with the particular entry is performed. Thereafter, in response to receipt of the second cache operation request, a determination is made whether servicing the second cache operation request requires replacement of one of the plurality of entries. In response to a determination that servicing of the second cache operation request requires replacement of one of the plurality of entries, an entry is identified for replacement. If the identified entry is the same as the particular entry specified by the first cache operation request, the identified entry is replaced only after servicing the first operation request.

Abstract: A case-based reasoning system is disclosed that includes a case database and a search engine. The case database is capable of storing a plurality of cases that each include one or more attributes that each have an associated match weight. Match weights of attributes in different cases are separately specified. In response to receipt of an incident including one or more input terms, the search engine scores the relative closeness of a selected case to the incident utilizing the match weights of attributes in the selected case that match input terms in the incident.

Abstract: An audio-video broadcast apparatus has non-volatile data storage that contains a file which includes at least one of audio and video data. In addition, the audio-video broadcast apparatus has an audio-video server coupled to the non-volatile data storage. The audio-video server broadcasts contents of the file and causes the non-volatile storage to delete a portion of the file from the non-volatile storage prior to the audio-video server broadcasting all of the contents of the file. In this manner, the amount of required non-volatile storage may be greatly reduced.

Abstract: A method and system are disclosed for handling exceptions generated by a particular processor among a number of processors within a multiprocessor data processing system. The data processing system includes a global queue from which threads are dispatched in a priority order for execution by the processors and a number of local dispatch flags, which are each associated with one of the processors. In response to an occurrence of an exception during execution of a particular thread by a particular processor, a state of the particular thread, which is at least partially defined by volatile data within the particular processor, is saved. A selected exception handler associated with the exception is then executed. Next, a determination is made whether resumption of the particular thread depends upon an occurrence of a specified event.

Abstract: A processor and method of interrupt handling in a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, in response to occurrence of an interrupt during emulation of a current guest instruction, an indication of a location in memory of the current guest instruction, an indication of a location in memory of a next guest instruction to be emulated, and an indication of a particular native instruction are stored. After an interrupt handler is executed, emulation is resumed by executing native instructions beginning with the particular native instruction. In response to execution of a native instruction of a first type before execution of a native instruction of a second type, the current guest instruction is fetched from memory.

Abstract: A data processing system includes at least one processor and data storage containing an array including N records having value-ordered entries. To find an entry matching a search value, W, a number of records to be searched, is set equal to N, and each of the W records is assigned to either a first set or a second set, where the first set includes X/2 of the W records and X is a smallest power of 2 equal to or greater than W. In response to a determination that the search value precedes the first record within the second set, a binary search of the first set of records is performed to identify a record including an matching entry. If the first entry of the first record within the second set matches the search value, the first record within the second set is identified.

Abstract: The present invention provides a performance monitor including a threshold indicator, a granularity indicator, an event detector, and an event counter. The threshold indicator indicates a number of threshold increments, which each correspond to a number of occurrences of a first event. The granularity indicator indicates the number of occurrences of the first event corresponding to each of the threshold increments indicated by the threshold indicator. The granularity indicator has at least a first state and a second state such that the granularity indicator indicates that a first number of occurrences of the first event correspond to a threshold increment in the first state and that a different second number of occurrences of the first event correspond to a threshold increment in the second state.

Abstract: A processor and method for tracking instruction execution within a processor are described. The processor includes at least one execution unit that executes instructions and an instruction status indicator that dynamically indicates a status of an instruction during processing. The instruction status indicator has at least a first state to which the instruction status indicator is set in order to indicate that execution of the instruction is stalled. In one embodiment, the processor further includes a reason code indicator associated with the instruction status indicator that specifies an event occurrence that caused the indicated instruction status. In another embodiment, the processor further includes a history buffer that indicates the number of processor cycles that the status indicated by the instruction status indicator has remained unchanged.

Abstract: A data processing system and method of preparing a presentation-ready document are described. In response to receipt of a document description that includes at least one Page Description Language (PDL) instruction and specifies both fixed data and variable data, the one or more PDL instructions are processed to produce separate presentation-ready images of the fixed data and the variable data. In addition, a bookticket specifying an arrangement of the presentation-ready images of the fixed data and the variable data is automatically generated. In response to receipt of the bookticket, a presentation-ready document is built that includes the presentation-ready images of the fixed data and the variable data in the arrangement specified by the bookticket. In one embodiment of the present invention, the document description specifies the fixed data of the document utilizing a PDL form operator.

Abstract: A processor and method of executing a program within a processor are provided. According to the method, a plurality of program instructions comprising a program and a set of auxiliary instructions are stored. An instruction stream including selected ones of the plurality of program instructions is supplied to the processor. In response to the processor processing a program instruction within the instruction stream that has an associated auxiliary instruction within the set of auxiliary instructions, the associated auxiliary instruction is automatically inserted within the instruction stream and the associated auxiliary instruction is executed within the processor.

Abstract: A data processing system and method of communicating data in a data processing system are described. The data processing system includes a communication network to which a plurality of devices are coupled. At least one device among the plurality of devices coupled to the communication network includes mastering circuitry and snooping circuitry. According to the method, a first timing signal having a first frequency and a second timing signal having a second frequency different from the first frequency are generated. Communication transactions on the communication network are initiated utilizing the mastering circuitry, which operates in response to the first timing signal, and are monitored utilizing the snooping circuitry, which operates in response to the second timing signal.