Abstract: A series of guest instructions including at least one guest branch instruction and other guest instructions are stored in memory. In addition, one or more semantic routines that are formed of native instructions and that may be utilized to emulate the series of guest instructions are stored in memory. For each other guest instruction in the series of guest instructions, an entry is stored in a multiple-entry queue in order of receipt of the other guest instructions. Each entry includes an indication of a location in memory of at least one semantic routine and a condition field indicating conditions that may be set or reset by the associated guest instruction. In response to the entries in the multiple-entry queue, the series of guest instructions are emulated in the processor by using the entries to access and execute selected ones of the one or more semantic routines.

Abstract: A processor and method of operating a processor which has a native instruction set and emulates instructions in a guest instruction set are described. According to the method, a series of guest instructions from the guest instruction set are stored in memory. The series includes a guest memory access instruction that indicates a guest logical address in guest address space. For each guest instruction in the series, a semantic routine of native instructions from the native instruction set is stored in memory. The semantic routines, which utilize native addresses in native address space, can be executed in order to emulate the guest instructions. In response to receipt of the guest memory access instruction for emulation, the guest logical address is translated into a guest real address, which is thereafter translated into a native physical address. A semantic routine that emulates the guest memory access instruction is then executed utilizing the native physical address.

Abstract: A method and data processing system for emulating a program are disclosed. According to the present invention, the data processing system runs under a first operating system and emulates the execution of a program under a second operating system within a second data processing system. The data processing system includes a memory which stores at least a portion of the first operating system and an emulator comprising a plurality of routines which each emulate an instruction utilized by the first operating system. The memory further includes a simulated mass storage data area which stores at least a portion of the program and a simulated main memory data area. The data processing system further includes a processor which executes instructions within the program under the first operating system by emulation. According to the present invention, the emulator accesses instructions of the program directly from the simulated mass storage data area to minimize emulation overhead.

Abstract: A method and system for automatically performing one or more operations on multiple computer systems within a cluster are disclosed. In accordance with the present invention, a begin operations command construct is defined within an input file. In addition, an input command indicating one or more operations to be performed on at least two computer systems within the cluster and an end operations command construct are defined. In response to a selected input, one or more operations indicated by the input command are automatically performed on at least two computer systems. In accordance with one embodiment, the begin operations command construct indicates selected computer systems within the cluster on which the one or more operations are to be performed and whether the operations are to be performed on the selected computer systems serially or in parallel.

Abstract: A data processing system and method of communicating data are provided. The data processing system includes a communication network to which a number of devices are coupled. According to the method, a timing signal having a selectable frequency is generated. Data is then communicated across the communication network between two of the devices in response to the selectable frequency of the timing signal. Thus, data is communicated at a first rate in response to the selectable frequency being set to a first frequency and is communicated at a second rate in response to the selectable frequency being set to a second frequency. In one embodiment, at least one of the devices includes communication control logic that can be selectively operated at the fixed-frequency of a clock signal.

Abstract: A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is assigned a current priority, at least the highest current priority being determined substantially randomly with respect to previous priorities of the requestors. In response to the current priorities of the requestors, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.

Abstract: A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is associated with a priority weight that indicates a probability that the associated requester will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requesters. In response to the current priorities of the requesters, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.

Abstract: A signal multiplier is provided for use in multiplying an analog differential signal. The analog differential signal is defined by a first analog attribute and a second analog attribute. Preferably, a means is provided for generating a first current which corresponds to the first analog attribute. Additionally, a means is provided for generating a second current which corresponds to the second analog attribute. A first amplifier member is provided for receiving the first current as an input and providing as an output a multiple of the first current. Additionally, a second amplifier is provided for receiving the second current as an input and producing as an output a multiple of the second current. A tuneable multiplier member is provided for determining the multiple over a predetermined range of multiples. A means for maintaining a substantially linear response of the signal multiplier is also provided.

Abstract: A method and system are described, which utilize timing analysis to verify a digital circuit design that includes a plurality of dynamic logic circuit cells employing diverse circuit techniques and that may also include static logic circuit cells. For each dynamic circuit cell, a set of timing constraints is defined based upon the circuit technique employed by the associated dynamic logic circuit cell. Each timing constraint prevents a possible mode of failure of the associated dynamic logic circuit cell. The digital circuit design is then verified. The verification includes a determination of whether or not each dynamic logic circuit cell satisfies its respective set of timing constraints while connected to the other circuit cells. In an embodiment in which the digital circuit design includes a static logic circuit cell, the verification includes a verification that the static logic circuit cell has a correct inversion relationship between its input and output.

Abstract: A method and system for modeling the behavior of a circuit are disclosed. A list specifying a plurality of transistors within the circuit and interconnections between the plurality of transistors is provided. Each fan node within the circuit is identified, where a fan node is defined as a point of interconnection between two or more of the plurality of transistors from which multiple nonredundant current paths to power, ground, or an input of the circuit exist. A fan node equation set is constructed that expresses a logical state of each fan node of the circuit in response to various transistor gate signal states. In addition, an output node equation is constructed that expresses a logical state of an output node of the circuit in terms of selected fan node logical states and specified transistor gate signal states.

Abstract: An operating system for manipulating the orientation of an output image of a data processing system provides operating system support to rotate an image output to a device driver at rendering time for printing in portrait or landscape mode and for displaying the image in increments of 90 decree rotations. A user or system sets a rotation for all output images sent to the peripheral device, regardless of what application provides the image, and the operating system performs the rotation on all output images sent to the particular output device.

Abstract: A method and system for constructing a program are provided. According to the method, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.

Abstract: A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be written to a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes the multiple-register instruction, such that at least two data words among the plurality of data words are written to at least two corresponding registers among the plurality of registers during a single cycle of the processor.

Abstract: A built-in self-test (BIST) apparatus and method for testing an integrated circuit are disclosed which enable capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. In addition, the BIST apparatus includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus further includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure.

Abstract: A remote program monitor method and system using a system-under-test microcontroller for self-debug comprises a system-under-test (SUT) that includes a read-only memory (ROM) and a microcontroller for executing a program under test. The microcontroller has an interrupt input, wherein one or more enable debugger signals received at the interrupt input causes the microcontroller to execute a debugger program contained in the ROM. The SUT is connected with a host computer over a standard serial connection. When the SUT receives one or more debugger signals as an interrupt input, the signal causes the microcontroller to execute a debugger program contained in the ROM.

Abstract: A processor and method for speculatively executing a branch instruction are disclosed. The processor includes a branch prediction unit for predicting a resolution of a speculative branch instruction, which is selectively configurable such that resolution of the speculative branch instruction is predicted in response to only an address of the speculative branch instruction or in response to branch history of at least one previously executed branch instruction. The processor also includes an address calculation unit for determining a target address in response to the predicted resolution of the speculative branch instruction. In one embodiment, the processor further includes configuration logic for dynamically configuring the branch prediction logic.

Abstract: A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the bus which performs bus transactions utilizing n-byte packets of data. An adaptor is electrically coupled between the first processor and the bus which converts n-byte packets of data input from the bus to m-byte packets of data, and converts m-byte packets of data input from the first processor to n-byte packets of data, thereby enabling the first processor to transmit data to and receive data from the bus utilizing m-byte packets of data. In a second aspect of the present invention, a method and system are provided for arbitrating between two bus masters having disparate bus acquisition protocols. In response to a second bus master asserting a bus request when a first bus master controls the bus, control of the bus is removed from the first bus master.

Abstract: A method and system in a data processing system for efficiently interfacing with cache memory by allowing a fetcher to read from cache memory while a plurality of data words or instructions are being loaded into the cache. A request is made by a bus interface unit to load a plurality of instructions or data words into a cache. In response to each individual instruction or data word being loaded into the cache by the bus interface unit, there is an indication that the individual one of said plurality of instructions or data words is valid. Once a desired instruction or data word has an indication that it is valid, the fetcher is allowed to complete a fetch operation prior to all of the instructions or data words being loaded into cache. In one embodiment, a group of invalid tag bits may be utilized to indicate to the fetcher that individual ones of a group of instructions or data words are valid in cache after being written into cache by the bus interface unit.

Abstract: A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requestors that share the resource. Each of the requestors is dynamically associated with a priority weight in response to events in the data processing system. The priority weight indicates a probability that the associated requestor will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requestors. In response to the current priorities of the requestors, a request for access to the resource is granted.

Abstract: An integrated circuit chip package having an electrical contact configurable for either signal or power/ground and a method for constructing the integrated circuit chip package are disclosed. The integrated circuit chip package includes a substrate for supporting an integrated circuit chip and a dedicated conductor for supplying voltage to the integrated circuit chip. A configurable contact is attached to a surface of the substrate. The integrated circuit chip package further includes a signal connection for electrically connecting a signal connector of an integrated circuit chip and the configurable contact. A removable connector electrically connects the configurable contact and the dedicated conductor, thereby enabling the configurable contact to be configured as either a signal or power/ground contact depending upon the absence or presence of the electrical connection between the configurable contact and the dedicated conductor provided by the removable connector.