Abstract: A circuit for providing decision feedback equalization uses a variable gain differential amplifier as a level detector and variable gain adjustment to provide nondelayed positive feedback and bit time delayed intersymbol interference compensating feedback to both enhance the amplitude of the present bit and reduce the intersymbol interference of one or more prior bits in a pulse bit stream.
Abstract: A universal gate array is illustrated using a specific pattern of CMOS (Complementary Metal Oxide Silicon) Transistors in an array which provides a high degree of board utilization in the layout of small runs of integrated circuits where the high cost of completely customized boards is unacceptable. The array comprises a continuing pattern of two sets of three (3) series connected transistors in a cell surrounded on all four sides by cells each containing two single transistor gates of each channel type.
Abstract: A high current low impedance antenna having an electrically short monopole radiation pattern is provided by shielding at least one of the segments or legs of a loop antenna so that the shielded leg has no cancelation effects and thereby produces the uniform radiation pattern of a short monopole antenna.
Abstract: The aftermath of a nuclear explosion generates a large amount of heat or infrared energy. When this heat is received by a parabolic reflector type antenna, the level of heat concentrated on the focal area of the feed is very intense. The present invention utilizes a highly heat conductive ceramic plug between the splash plate at the focal area of the feed and the waveguide so that heat can be readily conducted away from the splash plate and thereby minimize operational destruction of this splash plate due to thermal overload. The heat conductor material is a ceramic which is substantially transparent to RF signals being received by, or transmitted from the waveguide of the antenna system.
Type:
Grant
Filed:
May 19, 1983
Date of Patent:
March 19, 1985
Assignee:
Rockwell International Corporation
Inventors:
Ted A. Dumas, Maarten Vet, Sam K. Buchmeyer
Abstract: A variable transformer is illustrated to be used primarily with high frequency transistors and other high frequency amplifying means to provide optimum impedance matching characteristics for individual transistors in a circuit rather than trying to design a given circuit to be universally applicable to a range of transistor characteristic values.
Abstract: Asymmetrical time division multiplex switch for use in a nonblocking switch matrix. This design reduces parts required to configure the switch matrix since the prior art typically uses symmetrical switches wherein one of the inputs and outputs of a plurality of switches are connected in parallel to perform the total switch matrix function. The asymmetrical design reduces parts count and accordingly increases reliability of the total device.
Abstract: Phase shifting apparatus is illustrated using a feedback loop to monitor the frequency and correct the phase shifting mechanism so that the desired amount of phase shift will occur at all frequencies. The phase shifter comprises a multistage storage means which samples the incoming signal periodically and outputs this information after a time delay. This time delay will vary for a given amount of phase shift depending upon the frequency. Thus, the feedback loop adjusts the sampling time whereby the time period of the sample times is electrically correct.
Abstract: The present comparator circuit uses a multiplexing operation in a feedback arrangement for balancing the current flow in one-half of a comparator circuit so that its effect is identical to the other half of the comparator circuit for a grounded input. In between the adjustment or "trim" operation, the same comparator and output circuitry are utilized to provide an indication of which of two input signals are greater. As designed, the circuit substantially eliminates unbalance problems due to temperature, device parameter variations due to processing, aging of these parameters and load unbalance conditions, as well as minimizing transistor noise in the output.
Abstract: An approach to measuring the phase difference between two signals which automatically compensates for errors due to unequal DC offsets between the two channels of phase derived signal circuitry due to aging or temperature variations of components in these circuits by measuring the positive and negative half cycle time periods of the two signals whose phase is being compared as well as measuring the time difference between the same phase point on each of the two signals and combining this information in accordance with an algorithm set forth herein to obtain a phase measurement. The swapping of the signal paths on a periodic basis and averaging of the results is also used to eliminate errors due to signal processing variations in one of the signal paths as compared to the other signal path.
Abstract: A phase controlled signal generator using a cyclical counter with preset and reset control terminals to provide a continually advancing digital signal. This digital signal is converted in a sine table PROM and D to A converter to a sine wave signal which signal has a phase shift with respect to a reference in accordance with a phase control preset input and which signal can be periodically synchronized to a given starting phase to maintain signal stability or Doppler frequency shift.
Abstract: A printed hybrid quadrature 3 dB signal coupler using discrete components for the capacitive coupling and plated through holes to effect an approximation of twisted wire coupling whereby the completed product occupies much less physical space on a printed circuit board than the normal quarter-wavelength coupler.
Abstract: Microstrip transistor characteristic matching apparatus is illustrated which can be altered as to design frequency, phase of reflection signal coefficient and magnitude of reflection coefficient to optimize signal transmission to or from a given transistor. After adjustment, the apparatus can be analyzed to quickly determine the characteristics required for an in-circuit commercial version of such a device.
Abstract: The present invention pertains to a display utilizing a plurality of display prisms in a single device each of which can be separately actuated so that there can be more messages available to a user than surfaces on the prisms due to the interaction of messages on a cooperative basis.
Abstract: It has been determined that if the level of the current input to a feedback stabilized driver amplifier circuit is compared with the level of the current output by the amplifier portion of this circuit, the ratio of the two currents is indicative of the condition of a load connected to the circuit. If the load comprises one or more impedances all of the same value, the ratio obtained will determine not only whether or not the load is open or short circuited but how many of the standard value loads are connected in parallel.
Abstract: A VOR bearing measurement scheme wherein the received 30 hertz reference signal is delayed a fixed time to produce an approximately 90 degree phase shifted reference signal. The reference is multiplied by the phase shifted, itself and the variable signals to produce first, second and fourth signals. The variable signal is then multiplied by the phase shifted signal to produce the third signal. The bearing is then indicative of the ratio of filtered third and fourth signals less the ratio of filtered first and second signals.
Abstract: Apparatus as disclosed which comprises a register normally operable in the parallel data in/parallel data out mode but which has control mechanisms for allowing it to be converted to a serial data in/serial data out register. This register comprises part of a register based state machine. When the register is locked in a given mode so that a predefined control bit pattern is maintained within the register while the rest of the state machine operates in a normal manner, the control bit pattern is iteratively executed which in turn allows the use of an oscilloscope to observe signals in the signal transmission path of the state machine.
Abstract: A logical AND and logical OR gate are utilized in conjunction with two signals forming bits to be added for ascertaining the value of generate and propagate signals. The generate signal is passed to the output whenever the carry input is a logic zero and the propagate signal is supplied to the output whenever the carry signal is a logic one. This simplification of the approach to generating ripple carry signals substantially reduces the number of transistor to a value of about one-half that utilized in the prior art.
Abstract: Synchronously clocked gating apparatus is illustrated for time multiplexing signals into and out of a register simultaneously whereby a single pin can be utilized for the two sets of data transfer rather than the two pins required in the prior art.
Abstract: When a state machine such as a computer is inoperative, the flow of data can occur in so many different ways that it is at times difficult to ascertain the portions of the state machine that are causing the problems. Whether the problems are caused by original design or later failure of components, the present invention can determine at least the general area of the problem and often the specific bit introducing the problem, by setting a predefined control bit pattern into a register and ascertaining whether or not the bit pattern returned to the register after a predefined sequence of operations matches design expectations. As illustrated, this may take the form of serially inserting data into a normally parallel operated register to form the predefined control bit pattern, which then is applied to a sequencer whose output address is used to address a word in ROM, and the addressed word as well as the address itself, is loaded into the register.
Abstract: Lookahead carry circuitry is provided for use with the consecutive bit stages of a digital adder whereby the computational throughput of an arithmetic logic unit can be increased (in other words reduced in time of operation). This is accomplished by reducing the number of gates required in the serial switching path to minimize the time delay for generation of carry output signals.