Abstract: An assembly for mounting a roll of paper or Mylar.RTM. film having a hollow core includes a radially expanding core insert at each end of the roll and a core insert support, mountable to a support structure, to support, position and apply a drag force to the paper roll. Each core insert has a radially expandable inner end which is expanded within the core to secure the insert in place. The outer end of the core insert extends beyond the edge of the paper roll. The core insert support includes a pair of arcuate contact surfaces and an adjustable spring biased brake shoe mounted to a frame. The brake shoe presses the outer end of the core insert against the contact surfaces to create a suitable drag on the paper roll. A flipper is pivotally mounted to the frame for movement between free movement and blocking positions to permit or prevent the core inserts from being removed from the core insert supports. Each flipper also axially biases the core insert towards the other flipper.

Abstract: A digital test system for generating a test signal in the form of an amplitude and/or phase modulated sinusoidal signal at a given carrier frequency is disclosed. Arbitrary amplitude and phase modulation functions may be selected and are provided to the system in the form of digitally encoded data streams. The system does not require a digital multiplier. A signal in the form of an unmodulated carrier signal may also be generated.

Abstract: A system for increasing the accuracy and resolution of an ADC comprising a digital filter connected to the output of the ADC, a system clock for providing a digital filter clock signal, a low/pass filter/amplifier for generating a large-scale, rapidly varying dither signal fdrom the digital filter clock signal, and a summing circuit for adding the dither signal to a test signal connected to the input of the ADC.

Abstract: A color image processing system is described which provides more realistic hard copy color images from composite video system input signals than previously available. The image processing system includes a synchronization separator 20 which operates to separate the synchronization pulses from the analog video information supplied to it. The analog video information is then converted to digital form by an analog-to-digital converter. The converter operates under control of a time base generator 100, including a programmable delay line 300, which receives synchronization pulses from the synchronization separator, and following a programmable time delay supplies a control pulse to the converter to cause it to sample the analog waveform and convert it to digital format. Once the signal is digitized, it is converted from an additive color system to a subtractive one end enhanced before being supplied to the color plotter 8.

Abstract: Apparatus for delaying an electrical signal includes a sequence of stages, each for delaying the signal. A coarser stage delays the signal by multiples of a predetermined fundamental delay interval and a finer stage provides for fine adjustment of the delay. The fine stage includes an integral number N of delay elements, the total providing a delay interval greater than the fundamental delay interval, whereby the fine delay intervals compensate for fabrication tolerances to enable accurate calibration of the combined system by post-fabrication measurement. In one implementation each delay stage includes a tapped transmission line to provide delay intervals, in another a ramp generator is used.

Abstract: A method of calibrating a feed forward, DAC post-correction system. The method includes fitting the Walsh co-efficiencts of a DAC transfer function to a straight line in the log domain. The deviation of these terms in the log domain is utilized to compute Walsh correction terms for use in the post correction system.

Abstract: An image processing system includes a synchronization separator 20 which operates to separate the synchronization pulses from the analog video information supplied. The separator includes an amplifier with a pair of input terminals. The video is coupled to one of the input terminals and a feedback loop coupled between an output terminal and the other input terminal. In this manner the negative synchronization pulses may be amplified while the positive video signals are limited. The extracted sync signal is used to control an analog-to-digital converter 70. The analog video information is then converted to digital form by an analog-to-digital converter. The converter operates under control of a time base generator 100, including a programmable delay line 300, which receives synchronization pulses from the synchronization separator, and following a programmable time delay supplies a control pulse to the converter to cause it to sample the analog waveform and convert it to digital format.

Abstract: A circuit technique for stabilizing the timing of signals at an output node of a gate, despite substantial variations in temperature. In a gate having a switching portion and an emitter follower, the temperature-dependence of the gate delay within the switching portion may be offset by suitable control of the temperature characteristics of the load current source supplying the emitter follower output node. The load current source comprises a current source resistor, a current source transistor having its collector coupled to the output node, and a reference voltage source. The voltage source, rather than having a zero temperature coefficient as in known temperature-compensated configurations, is configured to have a temperature coefficient chosen to provide a temperature dependence in the delay through the emitter follower that offsets the temperature dependence of the delay through the switching portion so that the total gate delay is substantially temperature-independent.

Abstract: A high speed voltage comparator circuit is disclosed which accepts a wide range of input potentials CBO1 and compares them with four potential levels CRH, CRL, CRIH, and CRIL. Each comparator includes input transistors Q103 and Q104, one of which is connected to the reference potential and the other is connected to the unknown potential. The emitters of the input transistors Q103 and Q104 are connected together through a resistor R105, and each emitter is connected to a current source, Q105 and Q107 respectively. A third current source Q106 is coupled to diodes D101 and D102 which are connected to the emitters of transistors Q103 and Q104 respectively. The difference between the reference potential and the unknown potential will forward bias one of the diodes and reverse bias the other. The resulting difference in emitter current between the input transistors Q103 and Q104 is detected by an output stage to indicate the relative magnitudes of the reference potential and the unknown potential.

Abstract: A plurality of test signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative amplitude of the response signal with respect to a programmed reference level. The digitally programmed source is included for providing gated voltage-current crossover forcing functions during functional testing to minimize the disturbance when the device being tested is connected and to protect out of tolerance devices. Programmable voltage and current values define a pass window to assure a non-ambiguous go/no-go result during testing.

Abstract: A plurality of signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals representing logic states or other parameters onto input pins of the device under test. The responses to the stimuli signals are monitored while the device is being tested. Each signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a device power supply connected to the node for supplying a test bias signal, a comparison circuit connected to the node for indicating the relative magnitude of the test bias signal with respect to the bias level at the node, and a latch circuit responsive to the output signal produced by the comparison circuit. The device power supply is included for providing test bias signals to test power drain during functional testing. The transitions of the device power supply are monitored and latched for providing a record of the power drain of the device being tested.

Abstract: A formatting circuit for a high speed integrated circuit test system controls the application of timed data pulses to the input terminals of the device being tested, generates strobe signals to control comparators connected to the output terminals of the device being tested, and provides circuitry to decode error signals received from the device being tested. The formatting circuit routes all critical signal paths to the device under test over separate signal lines, thereby allowing compensation for the different propagation delay of each signal path. The input transitions and output strobe signals for the device being tested are not fixed in time with respect to the system clock, but are referenced to it. This enables drive data cycles and compare data cycles to be less dependent on the system clock, and permits them to overlap and cross test period boundaries.

Abstract: A plurality of test signal applying and response signal monitoring circuits is coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and response signal monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative magnitude of the response signal with respect to a programmed reference level on a repetitive basis during testing to increase test rate. Other features are also disclosed.

Abstract: A circuit technique for eliminating history-dependent skew and distortion of signals as they propagate through multiple gate stages in critical timing paths. It has been discovered that spurious effects can be attributed to signal coupling between stages, and that such coupling may be reduced by providing separate threshold voltage supplies for the critical gates. Each of the first and second gate stages comprises first and second transistors having their respective emitters coupled to a common circuit point, a current source coupled to the common circuit point to provide current flow through the transistors, with the relative current flow through said transistors being determined by the relative voltage levels at the respective bases. The output signal is taken from the collector of one of the transistors. First and second threshold voltage sources are coupled to the respective bases of the second transistors of the first and second gate stages.