Abstract: A master device (11) can access slave devices (12) either speculatively or non-speculatively. The slave devices (12) can be either non-hazardous devices or hazardous devices which exhibit status changes on reading. The master device (11) issues an access request including information as to whether the request is speculative or non-speculative, the slave device (12) then responds to the master device (11) with a negative acknowledgment that access is denied if the access request is speculative and the slave device (12) is hazardous. Otherwise, if the slave device (12) can deal with the request, a positive acknowledgment is sent. If the master device (11) receives a negative acknowledgment, it continues to reissue updated access requests until a positive acknowledgment is received.

Abstract: A Distinctness Measurement (DM) is determined (16) for Finite State Machine (FSM) state transitions. The DM is used to identify Unique Input/Output Sequence (UIO) Sets (63) that uniquely identify FSM (33) states. UIO Set members are combined with FSM transitions to form Test Subsequences (TS). Test Subsequences are connected (64) into Hierarchical TS Graphs (65), which are merged (38). The merged TS Graph (39) is augmented (94) and Euler Toured (28) to generate Verification Test Sequences (VTS). A VTS (43) tests conformance of a Machine-Under-Test (14) against a FSM (33) model.

Abstract: A Target MCU is restored to a Target State. A Host Trace of Debug Commands is preserved as the Target MCU is driven from a known first state to the Target State by executing a series of Debug Commands. The Target MCU is then reinitialized to the known first state. The Debug Commands are read from the Host Trace and sent to a Modular Development System (MDS) for execution by the Target MCU until the Target MCU is again is driven to the Target State.

Abstract: A Host Debugger and a Modular Development System (MDS) are dynamically reconfigured. The Host Debugger queries the MDS for the identity of its Target MCU. The Host Debugger receives a message containing the Target MCU identity. The corresponding Host Debug and MDS environments are then loaded based on the received Target MCU identity.

Abstract: A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. If a membership function has a boundary with an infinite slope, the slope value is set equal to zero and the degree of membership is then set equal to a saturation value for those input values corresponding to the infinite slope boundary.

Abstract: A parser is dynamically reconfigured. Parse Control Records are read into memory. They are inserted into corresponding Parse Table Entries in a Parse Table in memory identified by a Parse Table Entry Identifier in each Parse Control Record. Each of the Parse Table Entries corresponds to a single command, and includes an ordered series of allowable parse states for that command. After a string of text has been tokenized into an ordered sequence of tokens, the ordered sequence of tokens is evaluated pursuant to the allowable parse states in the Parse Table Entries to determine whether the Text String has a valid syntax.

Abstract: A copy of data in a Host Computer is synchronized with a version located in Shared Memory in a Modular Development System (MDS). Whenever a change in one or more bits in a Line of Data in Shared Memory are detected, a MDS Line Dirty Flag is checked. If the Flag is not set, it is set and a message is sent to the Host Computer that the Line of Data is now dirty. Whenever the Host Computer receives this message for a Line of Data in its visible memory, it sends a request to the MDS to read that Line from Shared Memory and send it to the Host. Otherwise, a Host Line Dirty Flag is set. The Host Computer also sends a request to read a Line of Data when that Line of Data is scrolled onto a screen and the corresponding Host Line Dirty Flag is set.

Abstract: Measurement of the test coverage of digital simulation of electronic circuitry is obtained (54). A Composite Circuit Model (60) has two parts: a Target Circuit Model (64) and an Environment Circuit Model (62). The Environment Circuit Model (62) models the behavior of inputs to the Target Circuit (64). The Composite Circuit Model (60) is translated into implicit FSM representations utilizing BDDs. A State Bin Transition Relation is formed which represents allowable transitions among user-specified sets of states or State Bins, and a representation of the reachable State Bins is built (94). A comparison is made (102) between data accumulated over one or more simulations (40) of the Target Circuit (64) and the data contained in the State Bin Transition Relation and the representation of the reachable State Bins.

Abstract: A data processing system (20) allows a user of a pager to receive an electronic message in a language of their own choice rather than the language of a message sender. During operation, the data processing system is enabled to receive (12) an incoming message and, subsequently, detect a language of the incoming message. If the language is different than a default language of the user, the message is translated to a default language of the user (34). The message is then be displayed (40) on a screen of a paging device in the language preselected by the user or provided via a voice synthesizer (50) for an audio message. The choice of use of a visual display or use of the voice synthesizer is preselected by the user.

Abstract: A high speed multichannel HDLC framing machine (112) cycles through Time Division Multiplexed (TDM) channels identifying a channel table (188) for each channel. HDLC state, data to be framed, and a mask are loaded into registers (176, 178), and the framer/deframer (112) is activated. The framer/deframer (112) returns an updated HDLC state, status flags, and a framed code word. The framed code word is multiplexed in a FIFO queue (58) for output on the high speed TDM line (28). A high speed multichannel HDLC deframing machine (112) receives a series of code words from a FIFO queue (56). For each code word received, a corresponding channel table (188) is identified. HDLC state, the code word to be deframed and, a mask are loaded into registers (176, 178), and the framer/deframer (112) is activated. The framer/deframer returns an updated HDLC state, status flags, and potentially a deframed data word.

Abstract: Transparent Time Division Multiplexer (TDM) Superchannels including multiple time slots assigned to a single logical channel are synchronized between transmitter and receiver. For a given time slot in an idle logical channel (286), the transmitter only starts transmitting output if this is the first time slot assigned to the logical channel (288) and output is available for the logical channel (290). Starting to transmit output is postponed (289) if this is not the first time slot assigned to the logical channel. Correspondingly, the receiver only expects new data blocks to start in the first time slot assigned to the logical channel.

Abstract: A dynamically configurable equipment integration architecture automatically records on a Host Computer (10) statistics from operation of Factory Equipment (18) received from a GEM Interface Server (16). The format of relevant messages containing selected reports are described in a Configuration File (44). Reports are enabled by execution of a Sampling Plan (50). Messages containing the selected reports received from the GEM Interface Server (16) are translated into a Script (46) utilizing the Configuration File (44). Interpreting the Script (46) causes statistics contained in the reports to be written to an Output File (52) stored on Secondary Storage (30) on the Host Computer (10).

Abstract: Arctangents (tan.sup.-1) are calculated utilizing binary floating point numbers through much of the function's range by extracting into an Integer Register (54) as an index ("i") the exponent and a specified number of fraction bits from a Floating Point Register(s) (60). The index is utilized by an Integer Unit (52) to index into tables of polynomial coefficients and reference values. The floating point difference between the absolute value of the argument(s) and the reference value selected by the index is a polynomial linear term. The coefficients in the table entry selected by the index are multiplied in a Floating Point Unit (58) by integral powers of the linear term. The Floating Point Unit (58) then sums the high order polynomial terms. The zero.sup.th level term added to the product of the first level term multiplied by the linear term forms a "big" term.

Abstract: Rounding error can be reduced when evaluating binary floating point polynomials utilizing a Floating Point Unit (58) by first computing the sum of products of second and higher order polynomial terms. Next, the Floating Point Unit (58) adds a zero.sup.th level term to the product of a first order coefficient and an independent variable to form a "Big" term. The Floating Point Unit (58) calculates as a "Little" term the rounding error resulting from the computation of the "Big" term. The "Little" term is then added to the sum of products of higher order terms to form an "Intermediate" term. Finally, the Floating Point Unit (58) adds the "Big" term to the "Intermediate" term to form the polynomial result corrected by the rounding error introduced by the computation of the low order terms.

Abstract: Hierarchical Test Subsequence (TS) subgraphs and Finite State Machine (FSM) subgraphs are merged.Hierarchical FSM subgraphs are merged (82) by connecting FSM model (33) child subgraph transitions or graph edges with states or vertices in the FSM parent subgraph. Matching is done based on Input/Output sequences. This merging (82) is repeated until all FSM child subgraphs are merged into FSM childless subgraphs. FSM childless subgraphs are Merged FSM graphs (83).Hierarchical Test Subsequence (TS) subgraphs (65) are merged (38) by finding peer subgraphs for TS child subgraphs. TS micro-edges from module entry and to module exit are connected to peer level FSM model states or vertices identified by matching Input/Output sequences. This merging (38) is repeated until all TS child subgraphs are merged into TS childless subgraphs. TS childless subgraphs are Merged TS graphs (39).

Abstract: A method and apparatus for identifying framing bits embedded in an ATM frame significantly improves performance by logically comparing multiple bit slices in parallel to identify framing bits. Bits are received from a sequential input stream (64) to form an ordered collection of bits, included (66) in a frame bit history. The remainder of the bits separating framing bits are ignored (68). A second group of bits is received (70) to form another ordered collection of bits of the same size. This ordered collection of bits is included (74) in the frame bit history. Bits in the sequential input stream are again ignored (80). A third group of bits is received (82) to form another ordered collection of bits, and is included (88) in the frame bit history. The various ordered collections of bits saved in the frame bit history are logically compared (90) to determine (92) whether any of the corresponding bit slices could possibly constitute framing bits.

Abstract: A measurement of the distinctness of Finite State Machine (FSM) (33) model state transitions can expedite identification of Unique Input/Output Sequences (UIO) (63). The Input/Output (I/O) sequences associated with FSM model (33) state transitions are compared. Each different I/O sequence is replaced by a different label so that transitions with the same I/O sequence have the same label and transitions with different I/O sequences have different labels. A transformation of the count of the number of times that each label is found in the FSM model, or a subset thereof, is determined, and assigned to each corresponding transition as a Distinctness Measurement (58). This Distinctness Measurement can be used to expedite a depth-first search for Unique Input/Output Sequences (63).