Abstract: A method for forming a metal pattern on a substrate (11) includes forming a dielectric stack (14) on a major surface (12) of the substrate (11) and forming a mask (22) on the dielectric stack (14). The dielectric stack (14) includes an aluminum nitride layer (16) serving as an etch stop layer between two dielectric layers (15, 17). An opening is formed in the dielectric stack (14) via successive etching. The etching of the dielectric layer (15) between the aluminum nitride layer (16) and the substrate (11) undercuts the aluminum nitride layer (16). A metal layer (30) is deposited on the major surface through the opening via sputtering. The metal layer (30) on the major surface is distinctively separated from a metal layer (34) on the edge of the opening. The mask (22) is dissolved in a solvent, thereby lifting-off a metal layer (34) deposited on the mask (22).

Abstract: A heterojunction bipolar transistor (HBT) (30) is formed to have a germanium composition profile (46) in a base region (32) that improves the tolerance of the HBT device (30) to manufacturing variations and reduces the sensitivity to emitter/base biases. A first region (40) of essentially constant germanium composition is formed at the interface of an emitter region (34) and the base region (32). The germanium composition profile (46) also has a second region (41) in which the germanium composition is increased linearly to provide an acceleration field by reducing the band gap in this second region (41). The acceleration field reduces the transit time of carriers and increases the frequency response of the HBT device (30).

Abstract: A method for forming a unilateral, graded-channel field effect transistor and a transistor stock 200 that includes providing a substrate (10) with an overlying gate electrode (14, 16). A spacer (23) is formed on only the drain side of the electrode. A graded-channel region (36) is formed aligned to the source side of the electrode while the spacer protects the drain side of the channel region. Source/drain regions (38) are formed, the spacer is removed, and then a drain extension region (40) is formed aligned to the drain side of the electrode.

Abstract: A semiconductor substrate (15) is placed into a recessed area (12) of a support structure (10). A ring (20) is then placed on the support structure (10) to form a wafer holder (30) which provides support to the semiconductor substrate (15) during handling, transporting, or electrical testing operations. The recessed area (12) can also have a vacuum opening (13) and a vacuum groove (17) so a vacuum pressure can be applied to the backside of semiconductor substrate (15). This will correct for any warpage or bowing in the semiconductor substrate (15) so a planar surface is formed for the electrical testing operation. The wafer holder (30) also has a flat (16) so the wafer holder (30) can be aligned and processed like a wafer with a diameter larger than the semiconductor substrate (15).

Abstract: The programming time of a non-volatile memory cell (13) is reduced by forming the non-volatile memory cell (13) in a well region (12). The presence of the well region (12) increases the number of electrons that are present in a channel region (14) of the non-volatile memory cell (13). The number of electrons in the channel region (14) is also increased by placing a voltage potential on the well region (12) relative to a source region (15). The voltage differential will inject electrons into the well region (12), which increases the number of electrons in the channel region (14).

Abstract: A low voltage field effect transistor structure (20) is provided with a threshold voltage that is tolerant of process variations that alter the location of a source implant region (41). A first halo region (33) and a second halo region (36) are formed adjacent to source region (41) such that after subsequent thermal processing, a constant doping profile of opposite conductivity as source region (41) is formed in the channel region (23) adjacent the source region (41). The embodiments can be formed either adjacent to only the source region (41) to create a unilateral device, or the doping profile can be formed adjacent to both source region (41) and a drain region (40) to produce a bilateral device. An additional embodiment forms a second implant region in source region (41) to reduce junction leakage and capacitance.

Abstract: A method of forming a package assembly (10) including a package (12) that encapsulates an electronic die. A leadframe (30) has edge rails (32), and the die is disposed on the leadframe. The package is formed around the die to encapsulate it, and the leadframe is trimmed to provide a plurality of leads (14) protruding from a first side of the package. This trimming also provides a support (16) connected to a second side of the package. The support is bent to be substantially orthogonal to the common plane containing the leads. A mounting tip (26) on the support is thus disposed outside of the common plane. This support improves the rigidity and natural bending frequency of the package assembly.

Abstract: A semiconductor-on-insulator transistor (10) has a channel region (30) in a semiconductor film (16) under a gate insulating layer (26). The channel region has a top dopant concentration N.sub.T at a top surface (32) of the film that is significantly greater than a bottom dopant concentration N.sub.B at a bottom surface (34) of the film. This non-uniform doping profile provides an SOI device that operates in a fully-depleted mode, yet permits thicker films without a significant degradation of sub-threshold slope.

Abstract: A pressure sensor (32) having a transducer (34) disposed on a top surface of an active die (38). The transducer has a doped region (42), the active die is disposed on a mounting substrate (70), and an interconnect opening (48) is disposed at an edge (90) of the active die. A metal layer (50) is disposed in the interconnect opening and on the top surface of the active die to be in electrical contact with the doped region. A conductive bump (76) is disposed on the mounting substrate in electrical contact with the metal layer and a conductive trace (74) on the mounting substrate.

Abstract: A component integration structure (10) for a microwave system includes a silicon substrate (12) having a resistivity greater than about 2,000 ohm-cm. A first die (14) is disposed on the silicon substrate, and a first passive element (20) is disposed on the silicon substrate and electrically coupled to the first die. In addition, a second passive element (22) and a second die (16) may be disposed on the silicon substrate. The second passive element is electrically coupled to the first passive element. An integration method sorts each of a plurality of active devices for placement on either the first die or the substrate depending on which of two different processing flows has the most favorable characteristics for fabricating each particular device.

Abstract: Dopants from a diffusion source (16) are diffused into a product wafer (14) to form a uniform doping concentration within the product wafer (14). The source (16) has a thermal conductivity that is approximately equal to a thermal conductivity of the wafer (14). The source (16) is positioned near the wafer (14) thereby forming a space (23) between the source (16) and the wafer (14). Gas flow (26) through the space (23) is limited to a predetermined value in order to prevent disturbing dopant diffusion. The source (16) is heated to a predetermined temperature, then the wafer (14) is heated. Subsequently, the wafer (14) and the source (16) are cooled at substantially equal rates.

Abstract: A semiconductor device (10) is formed from a single leadframe (11) by aligning two electronic components (22,24) relative to each other. The leadframe (11) has two bonding regions (30,31), which are offset from each other, and interconnect bars (13) which are used to align the two bonding regions (30,31). After the electronic components (22,24) are mounted to their respective bonding regions (30,31), the interconnect bars (13) are bent downward or upward relative to the plane formed by the leadframe (11). The bending of the interconnect bars (13) will move the two electronic components (22,24) towards each other in the direction essentially parallel to the plane of the leadframe (11). A transparent mold (28) is then formed to encapsulate the electronic components (22,24). A body (29) is then formed around the transparent mold (28) and leads (19,20). A trim and form operation releases the semiconductor device (10) from the leadframe (11).

Abstract: A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

Abstract: A current limiter (15) is formed between a silicon substrate (10) and a source region (17) by a channel implant region (20). The channel implant region (20) is not modulated by a gate structure so the maximum voltage that can flow between the silicon substrate (10) and the source region (17) is determined by the doping profile of the ever-present channel implant region (20). A pinch-off structure (12) is used to form a depletion region which can support a large voltage potential between the silicon substrate (10) and the source region (17). In an alternate embodiment, a bipolar device is formed such that a limited current flow can be directed into a base region (32) which is used to modulate a current flow between silicon substrate (30) and an emitter region (38). Using the current limiters (15, 35) it is possible to form an AC current limiter (50) that will limit the current flow regardless of the polarity of the voltage placed across two terminals (51, 52).

Abstract: An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28), and the continuous plurality of n-type regions (14, 16, 26) fully isolates the p-type well (28) from the substrate (12) except that the continuous plurality of regions (14, 16, 26) comprises one or more p-type gaps (18) that electrically connect the p-type well (28) to the p-type substrate (12). The use of the gap (18) improves cross-talk suppression in mixed-mode integrated circuits at higher frequencies, for example greater than 50 MHz.

Abstract: A non-volatile memory cell (10) is provided employing two transistors (11, 12) connected in series. A floating gate structure (13), formed with a single polysilicon deposition, is shared by each transistor (11, 12) to store the logic condition of the memory cell (10). To program and erase the memory cell (10), a voltage potential is placed on the floating gate (13) which modulates the transistors (11, 12) so only one is conducting during read operations. The gate capacitance of the transistors (11, 12) is used to direct the movement of electrons on or off the floating gate structure (13) to place or remove the stored voltage potential. The two transistor memory cell (10) couples one of two voltage potentials as the output voltage so no sense amp or buffer circuitry is required. The memory cell (10) can be constructed using traditional CMOS processing methods since no additional process steps or device elements are required.

Abstract: A cap wafer (10) is used to package semiconductor devices on a device wafer (30). Successive etching processes form a plurality of partially etched cavities (27) extending from a front surface (11) of the cap wafer (10) into the cap wafer (10). The pattern of the partially etched cavities (27) is determined in accordance with the pattern of dies (32) on the device wafer (30). The cap wafer (10) is aligned with the device wafer (30) and bonded to the device wafer (30) using a glass frit as a bonding agent. After being bonded to the device wafer (30), the cap wafer (10) is thinned from the back surface (12) until the back surface (12) of the cap wafer (10) reaches the partially etched cavities (27). The device wafer (30) is then diced into distinct dies.

Abstract: A board (10) for testing an integrated circuit disposed on a semiconductor wafer. The board contains a plurality of substantially parallel signal layers (14) and power planes (16) that are supported and electrically isolated by a dielectric material (12). One or more constraint layers (18,20) are disposed in the dielectric material, and the constraint layers have a coefficient of thermal expansion of about 1-6 ppm/.degree.C. In a preferred embodiment, the dielectric material is a fluoropolymer with-a ceramic or silica filler, and the constraint layers are an iron-nickel alloy of about 30-40 percent nickel by weight. The board has thermal expansion characteristics substantially similar to silicon to ensure good contact to a silicon wafer during burn-in testing.

Abstract: A semiconductor device having electronic circuitry formed in a semiconductor substrate (11) and separated from an overlying metal interconnect layer (18,18') using a fluorinated polymer dielectric (14,14') . The fluorinated polymer layer (14,14') may be formed directly on metallic surfaces, or formed on a semiconductor or non-metallic surface using an adhesion promoter (13,13'). Once formed, the fluorinated polymer layer (14,14') can be patterned to provide vias, and covered with a patterned metal interconnect layer (18,18') .

Abstract: A method of forming leads and providing a final test of a semiconductor package including an electronic circuit therein, the package having unformed leads. A forming and testing station is provided including a support for receiving the package, and dies movably positioned adjacent the support for contacting and forming the leads with test equipment connected to the dies. The semiconductor package is positioned on the support, and the leads of the package are contacted with the dies to connect the test equipment to the leads for testing the electronic circuitry in the package and to form the leads with this contacting step as the final manufacturing step.