Abstract: A III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.

Abstract: The etching of a thin substrate (23) is performed using a holder (10). The holder (10) has a base (11) that has a cavity (20). The cavity (20) is pressurized to compensate for the pressure and stress that is applied to the substrate (23) by an etchant solution. The holder (10) also has a sequence of o-rings (22,24,26) that are used to hold the substrate (23) in place and to prevent etchant from leaking into the cavity (20) and attacking a bottom surface (32) of the substrate (23). The pressure necessary to hold the substrate (23) in place is applied by a cover ring (28) that is screwed onto the base (11).

Abstract: A chemical probe field effect transistor (10) for measuring surface potential as a function of temperature and used for chemical sensing. Source and drain regions (14, 16) in a semiconductor substrate (12) define a channel region (34). A gate insulating layer (18) covers the channel region, and a gate electrode layer (20) is disposed above the gate insulating layer to provide a gap (22) between the gate insulating layer and the gate electrode layer. This gap permits a fluid to contact an exposed surface (28) of the gate electrode layer. A heating layer (30) is disposed overlying the gate electrode layer to regulate its temperature. The surface potential of the gate electrode layer changes in response to the presence of certain chemicals in the contacting fluid.

Abstract: A capacitor (58) for an integrated circuit having a conductive trench (50), disposed below a bottom electrode layer (52), that electrically connects the bottom electrode layer to a semiconductor substrate (14, 16). The conductive trench eliminates the need for a top-side contact to the bottom electrode layer. The semiconductor substrate is, for example, connected to ground.

Abstract: A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride (17) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.

Abstract: A passive element structure and method for a microwave integrated circuit reduces signal propagation losses. In one approach, a passive element (10) has an insulating layer (12) overlying a silicon substrate (14). A metal layer (16) comprising a signal line (18) and a groundplane (20) is disposed overlying the insulating layer (12), and at least a portion of the metal layer (16) contacts the substrate (14) through at least one opening (22, 24) in the insulating layer (12). The silicon substrate (14) has a resistivity greater than 2,000 ohm-cm, and the passive element (10) preferably carries signals having frequencies greater than 500 MHz. Signal losses in the passive element (10) are minimized because the charge density at the surface (15) of the substrate (14) underlying the metal layer (16) is significantly reduced. In one example, the passive element (10) is a coplanar waveguide transmission line.

Abstract: A method for fabricating semiconductor substrates with resistivity below 0.02 ohm-cm is provided. This low resistivity is achieved by doping a silicon melt with a phosphorus concentrations above 1.times.10.sup.18. The silicon melt is also doped with a germanium concentration that is 1.5 to 2.5 times that of the phosphorus concentration and a stress and dislocation free crystalline boule is grown. Phosphorus in high concentrations will induce stress in the crystal lattice due to the difference in the atomic radius of silicon atoms versus phosphorus atoms. Germanium compensates for the atomic radius mismatch and also retards the diffusion of the phosphorus as the diffusion coefficient remains relatively constant with a doping of 1.times.10.sup.18 to 1.times.10.sup.21 atoms per cm.sup.3. This will retard phosphorus from diffusing into an overlying epitaxial layer and retard other layers formed on the substrate from being auto-doped.

Abstract: A method for setting the sensing polarity of a sensor device (10) uses a switching bridge (22) having a wheatstone bridge configuration that is coupled to a sensing element (20) such that the polarity of the sensor device can be set by creating two electrical opens, for example with laser trimming along a cut line (59, 66), in parallel branches (30, 31) of the switching bridge. These opens are formed after the sensor device has been fully processed.

Abstract: An enclosure (8) for an electronic device (26) such as, for example, an accelerometer. The enclosure (8) includes a conductive semiconductor substrate (12) underlying the electronic device (26), a conductive cap (16) overlying the electronic device (26), and a power supply (25) having one or more outputs (27, 29) each with a substantially fixed potential wherein one output is electrically coupled to the conductive semiconductor substrate (12) and another output to the conductive cap (16). In a preferred embodiment, substrate ( 12 ) and cap (16) are coupled to the same power supply output (27). This coupling substantially eliminates the adverse effects of parasitic capacitances of the substrate (12) and cap (16) to reduce measurement error and EMI when a capacitive accelerometer is used as the electronic device (26).

Abstract: An encapsulated microelectronic device (100) including a base (101) and a semiconductor device (305) having a top and a bottom. The bottom is attached to the base (101). The semiconductor device (105) has a thickness in the range from one-fourth to three-fourths of a millimeter and has a bottom metallization consisting of aluminum (407)/chromium (405)/nickel (403)/gold (401). The semiconductor device (305) has a contact (115) attached to the top. The encapsulated microelectronic device (100) has a molded top (120) surrounding the semiconductor device (305). The molded top (120) is made from low stress molding material.

Abstract: A sensing transducer (10,30) and a method therefor uses a Schottky junction (12) having a conductive layer (16) disposed on a semiconductor substrate (14). The conductive layer (16) is generally formed from the reaction of a metal with a portion of the semiconductor substrate (14). One example of the conductive layer (16) is a metal silicide layer. In one pressure sensing approach, a substantially constant reverse current (I.sub.1) is applied to the Schottky junction (12). The change in reverse output voltage of the junction (12) is proportional to the change in pressure on the junction (12) itself, and can thus be used to sense pressure. This output voltage change is significantly higher than that achieved with prior pressure transducers and permits the output signal of the transducer (10,30) according to the present invention to be substantially used without extra amplification or other conditioning.

Abstract: An encapsulated microelectronic device (100 ) including a base (101) and a semiconductor device (305) having a top and a bottom. The bottom is attached to the base (101). The semiconductor device (105) has a thickness in the range from one-fourth to three-fourths of a millimeter and has a bottom metallization consisting of aluminum (407)/chromium (405)/nickel (403)/gold (401). The semiconductor device (305) has a contact (115) attached to the top. The encapsulated microelectronic device (100) has a molded top (120) surrounding the semiconductor device (305 ). The molded top (120) is made from low stress molding material.

Abstract: A semiconductor device (8) has an insulating layer (16) overlying a semiconductor substrate (12). The insulating layer has a first opening that defines an aperture (18) extending from the insulating layer to the semiconductor substrate, and at least a first portion of a first conductive terminal (42) is disposed in the aperture. A second conductive terminal (52) has a second portion (28) disposed in the aperture. The second portion of the second conductive terminal is separated from the first conductive terminal by a composite dielectric layer including a nitride layer (32) and an oxide layer (30). In one approach, the oxide layer is formed by the oxidation of the second portion of the second conductive terminal.

Abstract: An x-ray lithography method for irradiating an object (14) to form a pattern thereon uses an x-ray mask (10) having a membrane (18). The membrane (18) has an open membrane surface (26), and x-ray radiation (16) is passed through the open membrane surface (26) to irradiate the object (14). During this irradiation, the open membrane surface (26) is substantially uniformly exposed to the x-ray radiation (16) so that stress-induced distortion of the membrane (18) is reduced.

Abstract: A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

Abstract: An opto-isolator (10) increases optical efficiency by using holographic elements (22,24,26) to direct a beam of light (34) through an optical waveguide (20). An opto-electronic transmitter (12) and receiver (16) are connected to the waveguide to be in alignment with the beam of light reflected by the holographic elements. The transmitter and receiver are disposed on separate leadframe portions (14,18), and the opto-isolator is surrounded by a package (32).

Abstract: A BiCMOS integrated circuit design having an oversized isolation area surrounding circuit elements which are non-scaleable is provided. The non-scaleable circuit elements can be removed from the layout, and the remaining scaleable elements shrunk by a CAD system. After shrinking the scaleable elements and the isolation area, the non-scaleable elements are returned to the layout at their original size, and located within the scaled-down isolation area.

Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36,38) is disposed between two of the fingers (16,18,20) for dividing current flow.

Abstract: A method of detecting defects (14, 16, 17, 44, 47, 49, and 51) in objects is presented. A first grey level image (18) of a first object (10) is formed and a second grey level image (19) of a second object (12) is formed. The first (18) and second (19) grey level images are converted to a first (21) and a second (22) edge feature image, respectively. The first edge feature image is dilated (26) and the second edge feature image is skeletonized (27). The dilated (26) and skeletonized images (27) are compared. An alternate method includes forming a grey level image (40) of an object. A principal axis of the grey level image is identified, and a shifted grey level image is formed by shifting the grey level image a distance along the principal axis. The grey level image (40) is then compared to the shifted grey level image.

Abstract: A semicondutor device having electronic circuitry formed in a semiconductor substrate (11) and separated from an overlying metal interconnect layer (18, 18') using a fluorinated polymer dielectric (14,14'). The fluorinated polymer layer (14,14') may be formed directly on metallic surfaces, or formed on a semiconductor or non-metallic surface using an adhesion promoter (13,13'). Once formed, the fluorinated polymer layer (14,14') can be patterned to provide vias, and covered with a patterned metal interconnect layer (18, 18').