Abstract: A method and apparatus to accelerate variable length decode is disclosed, including a method and an apparatus to initialize data structures. The initialization apparatus includes a start address storage region to receive a start address from a processor and a memory access engine coupled to the start address storage region. The memory access engine writes a predetermined pattern to a data structure located in a memory device. The data structure is defined by the start address stored in the start address storage region and is further defined by a predetermined data structure size.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: An embodiment of an integrated circuit die with staggered bond pads and optimized driver layout includes a staggered array of bond pads with an outer ring of bond pads and an inner ring of bond pads. Driver/ESD circuit cells for the outer ring of bond pads are located to the outside of the bond pads (between the outer ring of bond pads and the nearest die edge). The driver/ESD cells for the inner ring of bond pads are located to the inside of the bond pads (between the inner ring of bond pads and the die core). The integrated circuit die is coupled to a lead frame via bond wires.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt if no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: A combination precharge/activate command is utilized in order to make more efficient use of a command bus between a memory controller and a system memory. Upon receiving a precharge/activate command from the memory controller, the system memory makes a determination as to how to interpret the command depending on a page status. For an open page, the precharge/activate command is treated as a precharge command and then the system memory performs an activate with proper command timing using address and bank given during precharge/activate command. For a closed page, the precharge/activate command is treated as an activate command.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: An example embodiment of a computer system that includes a removable agent that can be removed or installed without powering down the system includes a fixed bus agent and the replaceable bus agent. The fixed bus agent and the replaceable bus agent are electrically coupled together by a presence detect signal, a synchronization signal, and a data bus. A deassertion of the presence detect signal indicates to the fixed bus agent that the removable bus agent has been disconnected and is no longer electrically coupled to the fixed bus agent. The fixed bus agent then tri-states its outputs and also prevents potentially invalid data from being delivered to the core circuitry of the fixed bus agent. An assertion of the presence detect signal indicates to the fixed bus agent that the replaceable bus agent is electrically connected to the fixed bus agent. In response to the assertion of the presence detect signal, the fixed bus agent and the replaceable bus agent enter reset periods.

Abstract: An embodiment of a graphics device that performs a vertical scale filter function using a single line buffer is disclosed. The graphics device includes a line buffer and a vertical scale filter function unit that produces an output of blended data. The line buffer stores the output of blended data and the vertical scale filter uses a next line of display data and a line of blended data stored in the line buffer to produce the output of blended data.

Abstract: An example embodiment of a method and apparatus for dynamically changing computer system configuration to improve software application performance includes a system logic device that implements at least two different configurations. The system logic device may change configuration depending on what software application is running. The system logic device can change configurations while the computer system is running and may change configurations in order to optimize performance for whatever application is currently running.

Abstract: A method and apparatus for improving read latency for processor to system memory read transactions is disclosed. One embodiment of a system logic device includes logic that assumes a transfer size of a predetermined length. In this manner, the system logic device can issue a read transaction request to system memory as soon as the read request address is delivered by the processor rather than waiting for the processor to deliver information indicating the transfer length. Once the actual transfer length information is delivered from the processor to the system logic device, the system logic device determines whether any of the data returned by the system memory needs to be purged before returning the requested data to the processor.

Abstract: A method and apparatus for managing overlay data requests are disclosed. One embodiment of an apparatus includes a request unit and a timer. A request is made by a graphics controller to the request unit for a line of overlay data. The request unit divides the request from the graphics controller into a series of smaller requests. The smaller requests are issued to a memory controller. Delays are inserted between each of the smaller requests in order to allow other system resources to more easily gain access to memory.

Abstract: An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first request path and a second request path. The memory controller further includes a graphics translational lookaside buffer that includes a cache. The graphics translational lookaside buffer issues an address fetch request to a memory interface when a graphics memory request received from the first request path or from the second request path misses the cache. The memory controller also includes a memory arbiter that includes a first request path cycle tracker and a second request path cycle tracker. The memory arbiter allows a request received from the second request path to be issued to the memory interface when a graphics memory request received from the first request path is stalled due to a graphics translational lookaside buffer cache miss.

Abstract: An example embodiment of a method and apparatus for reducing back-to-back voltage glitch on a high speed bus is described. A pre-driver circuit receives an input voltage signal whose voltage level swings from a logically low voltage level to a logically high voltage level where the logically low voltage level approximately equals VSS and the logically high voltage level approximately equals VCC. The pre-driver circuit reduces the magnitude of the voltage swing to create a signal that when delivered to a driver transistor ensures that the driver transistor will operate in its saturation region even when the voltage on the high speed bus is at its minimum specified voltage. When the driver transistor operates in its saturation region it can sink a constant current and provide a high output impedance.

Abstract: An embodiment of a system logic device for improving memory bandwidth utilization in a computer system with an isochronous data stream includes a FIFO for the isochronous data stream. The FIFO includes two watermarks. When the data level of the FIFO falls below a first watermark level, a low priority request is issued to a memory controller. If the data level of the FIFO falls below a second watermark level, a high priority memory request is issued to the memory controller. The low priority memory request is assigned the lowest priority level by the memory controller. The high priority request is assigned the highest priority level by the memory controller. The low priority request allows the isochronous data stream to retrieve small amounts of data from memory without negatively impacting overall system performance while the high priority request allows the isochronous data stream to retrieve larger amounts of data from memory within a fixed time in order to ensure that the FIFO never completely drains.

Abstract: A method for calibrating analog sensor measurements within a computer system is disclosed. The method includes the steps of generating an analog sensor measurement result, reading at least two values that define a curve from a memory device, and calculating a calibrated result using the analog sensor measurement result and the values that define the curve.

Abstract: In one embodiment of a method for recovering from a computer system lockup condition, an interrupt is generated to the computer system's operating system notifying the operating system of the lockup condition. An operating system interrupt handler is then executed. The interrupt handler performs at least one step to attempt to cure the lockup condition. If the interrupt handler fails to cure the lockup condition, the interrupt is regenerated to the operating system notifying the operating system of the lockup condition. The interrupt handler is then re-executed in response to the regeneration of the interrupt, with the interrupt handler performing a further step in attempting to cure the lockup condition.

Abstract: An embodiment of a memory controller that improves processor to graphics device throughput by reducing the frequency of retries of postable write transaction requests is disclosed. The memory controller includes a posted write buffer and a timeout counter. The memory controller is coupled to a processor via a host bus and is also coupled to a graphics device via a graphics bus. If the posted write buffer is unavailable when a first postable write transaction request is received by the memory controller, the memory controller stalls the host bus and waits for the posted write buffer to become available. If a second transaction request is received while the posted write buffers are unavailable, the timeout counter is initiated. If the posted write buffer becomes available before the timeout counter expires, the first postable write transaction request is completed.

Abstract: A memory controller with an integrated system management memory region is disclosed. The memory controller receives an SMI acknowledge signal from a processor. The processor then delivers a system management memory address to the memory controller. Instead of fetching SMI handler instructions from the address indicated by the processor, the memory controller instead fetches SMI handler instructions from its integrated system management memory region. At the end of the integrated system management memory's SMI handler, the processor is instructed to fetch instructions from the address originally specified by the processor. In this manner, a BIOS SMI routine may be executed after the integrated SMI routine is executed.

Abstract: An embodiment of an apparatus that saves power and improves performance in a pipeline using gated clocks is disclosed. The apparatus includes a clock signal and a first pipeline stage that includes a first data register, a first data valid register, and a first clock gate circuit. The apparatus also includes a second pipeline stage coupled to receive data from the first pipeline stage. The second pipeline stage includes a second data register, a second data valid register, and a second clock gate circuit. The second data register receives data from the first data register when the second clock gate circuit conducts the clock signal to the second data register. The second clock gate circuit conducts the clock signal if the first data valid register indicates that the first data register contains valid data. The second clock gate circuit does not conduct the clock signal to the second data register if the first data valid register indicates that the first data register contains invalid data.