Abstract: A negative charge pump circuit is disclosed. The pump circuit includes several stages, each stage including a switching transistor, a pull up diode, and a pull down diode. The pump circuit also includes a blocking transistor coupled between the gate terminal of the switching transistor and the pull down diode of the third stage. The gate terminal of the blocking transistor is electrically coupled to the source terminal of the switching transistor of the first stage where the first stage provides the output for the negative charge pump circuit. A voltage present at the output of the first stage is delivered to the gate terminal of the switching transistor of the third stage when a positive programming voltage is present at the output of the first stage in order to block the positive programming voltage from shorting to ground through the negative pump circuit.

Abstract: A method and apparatus to accelerate variable length decode is disclosed. The system includes a logic device to receive a bit stream of variable length encoded information. The logic device outputs a fixed length value corresponding to a variable length code received as part of the bit stream of the variable length encoded information. The system also includes a processor to receive the fixed length value. The processor to performs a write of a coefficient to a system memory device, the coefficient corresponding to the fixed length value received from the logic device.

Abstract: An embodiment of a method for terminating direct memory access transfers from system memory to a video device includes completing a current byte transfer from a graphics controller to a video device and then refraining from initiating any further write cycles associated with a DMA transfer to the video device. The graphics controller then allows uninterrupted or atomic read and write cycles to the video device. The graphics controller also completes any current read cycles on a system bus that had previously been initiated. The graphics controller then resets its DMA engine and invalidates all information in a first-in, first-out (FIFO) storage buffer.

Abstract: An embodiment of a graphics device that maintains load balance on a graphics bus when an upgrade graphics device is installed is disclosed. The embodiment includes load balancing buffers for the strobe compliment signals AD_STB0#, AD_STB1#, and SB_STB# on a 2× mode AGP graphics device. The load balancing buffers couple the 2× mode AGP graphics device to the strobe compliment signals AD_STB0#, AD_STB1#, and SB_STB#, but the load balancing buffers are not connected to any internal circuits within the 2× mode AGP graphics device. The load balancing buffers provide equal capacitive loading between the strobe signals AD_STB0, AD_STB1, and SB_STB and their compliment signals AD_STB0#, AD_STB1#, and SB_STB# when an upgrade 4× mode AGP graphics device is installed.

Abstract: One embodiment of an apparatus for communicating routing and attribute information for a transaction between hubs in a computer system is disclosed. The apparatus includes a data path input/output unit to output a packet header for a transaction. The packet header includes a transaction descriptor routing field to identify an initiating agent that initiated the transaction. The transaction descriptor routing field includes a hub identification portion and a pipe identification portion. The hub identification portion identifies a hub that contains the initiating agent. The pipe identification portion further identifies the initiating agent within the identified hub if the transaction has no ordering requirements with respect to a second agent in the identified hub.

Abstract: A programmable logic device that includes a voltage input and a detection circuit coupled to the voltage input is described. The detection circuit detects whether a voltage applied to the voltage input exceeds a predetermined value. The programmable logic device also includes a configuration circuit coupled to the detection circuit. The configuration circuit configures the programmable logic device to receive a current sufficient for program and erase operations through the voltage input in response to the detection circuit detecting that the voltage exceeds the predetermined value.

Abstract: A graphics device implemented in accordance with one embodiment of the invention includes a first request path to a local memory interface for low-priority read transactions and a second request path to the local memory interface for low-priority write transactions. The second request path is also used for read transactions received over a system bus. The graphics device further includes an arbiter that arbitrates between the first request path and the second request path, with the second request path having a higher priority than the first request path.

Abstract: A method and apparatus is disclosed for providing a reduced-capacitance transistor with ESD protection that can be fabricated using standard processes. The transistor includes a substrate, a source region formed in the substrate, and a well region also formed in the substrate. The transistor further includes a drain region having a first end region, a second end region, and a resistive region positioned between the first and second end regions. The drain region is formed at least partially in the well region. A drain contact is form on the first end region of the drain region. Additionally, a gate structure is included. The gate structure is formed on the substrate between the source region and the second end region of the drain region. The gate structure defines a channel region that couples the source region to the drain region.

Abstract: A method of fabricating minimum size and next-to-minimum size electrically conductive members using a litho-less process is disclosed. A substrate is provided, and a layer of gate dielectric material is formed on the substrate. A layer of electrically conductive material is formed over the gate dielectric material. A first mask is used to form a hard mask. A layer of first spacer material is deposited over the existing structures, and the layer of first spacer material is etched back to form spacers adjacent to the hard mask. The width of the first spacers determines the minimum size gate length. A layer of second spacer material is deposited over the existing structures, including the hard mask and first spacers. The layer of second spacer material is etched back to form a second set of spacers adjacent to the first spacers. The width of the first and second spacers together determine the next-to-minimum size gate length.

Abstract: A reset signal is asserted to a processor. In response to the reset signal, the processor normally performs an instruction fetch cycle to a predetermined address. If the processor fails to perform the instruction fetch cycle or fails to perform the fetch cycle to the predetermined address within a predetermined period of time, an indication is provided that the processor reset has failed.

Abstract: A timer is periodically reset by a software agent executing on a processor. If the timer is not reset within a predetermined period of time, an interrupt is generated. An interrupt handler then periodically resets the timer, and if the timer is not reset within an additional predetermined period of time, the computer system is partially reset.

Abstract: A method and apparatus for accessing and downloading information from the internet to a hand held computer system. The computer system includes a bus to which a processor, a display screen, input keys, and a flash memory are coupled. The flash memory stores an operating system for the computer system, search criteria, information corresponding to the search criteria downloaded from the internet, and display application software for displaying the information on the display screen.

Abstract: A system for accelerating instruction restart in a microprocessor. An instruction is fetched. The instruction is placed in a macro-instruction queue and sent to the decoder. The instruction is decoded in order to produce at least one micro-operation. The micro-operation is executed, and the microprocessor checks for instruction restart conditions. If an instruction restart condition is found, the instruction restart function is performed. The instruction restart function includes decoding the instruction stored in the macro-instruction queue and executing the corresponding micro-operations.

Abstract: A cascading transistor gate structure and method for fabricating the same are disclosed. A substrate is provided, and a layer of gate dielectric material is formed over the substrate. A layer of electrically conductive material is formed over the gate dielectric. A layer of hard mask material is formed on the layer of electrically conductive material. A photoresist mask is used to pattern the layer of hard mask material to form a hard mask. A layer of spacer material is deposited over the existing structures, and the layer of spacer material is etched to form a pair of spacers adjacent to the hard mask. The hard mask is removed, leaving the spacers. The layer of electrically conductive material is etched in alignment with the spacers. The spacers are then removed, revealing two transistor gates. A conductive region in formed in the substrate between the two gates. The two gates operate in tandem, yielding a cascading gate with an effective length that is the lengths of the two gates combined.