Abstract: A method for finding a path in a network is disclosed. The network includes a plurality of nodes and a plurality of links and each one of the plurality of nodes is coupled to at least one other of the plurality of nodes by at least one of the plurality of links. Such a method generates at least one path cost data set and accessing the path cost data set to provide the requisite path information. The path cost data set represents a path cost between a root node of the nodes and destination node of the nodes. The path begins at the root node and ends at the destination node. The generation and accessing operations are performed in such a manner that a minimum-hop path and a minimum-cost path can be determined from the at least one path cost data set. The minimum-hop path represents a path between the root node and the destination node having a minimum number of hops. The minimum-cost path represents a path between the root node and the destination node having a minimum cost.

Abstract: An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. The decoder generates a Bose-Chaudhuri-Hocquenghem (BCH) error polynomial in no more than 12 clock cycles. The decoder includes several Galois field multiply accumulators, and a state machine which controls the Galois field units. In the specific embodiment wherein the error-correction code is a BCH triple error-correcting code, four Galois field units are used to carry out only six equations to solve the error polynomial. The Galois field units are advantageously designed to complete a Galois field multiply/accumulate operation in a single clock cycle. The Galois field units may operate in multiply or addition pass-through modes.

Abstract: A programmable logic unit (e.g., an ASIC or FPGA) having a feedforward linear associative memory (LAM) neural network checking circuit which classifies input vectors to a faulty hardware block as either good or not good and, when a new input vector is classified as not good, blocks a corresponding output vector of the faulty hardware block, enables a software work-around for the new input vector, and accepts the software work-around input as the output vector of the programmable logic circuit. The feedforward LAM neural network checking circuit has a weight matrix whose elements are based on a set of known bad input vectors for said faulty hardware block. The feedforward LAM neural network checking circuit may update the weight matrix online using one or more additional bad input vectors. A discrete Hopfield algorithm is used to calculate the weight matrix W.

Abstract: A method for automated technical support in a computer network having a client machine, and at least one server from which live help is available. The method begins initiates a guided self-help session in response to entry by a user of a problem area and description. During the self-help session, the user is provided with an option to escalate to live help. If the user exercises that option, the system automatically provides a support engineer at the server with a data stream summarizing the self-help session. During the live help, the support engineer may then repeat a portion of the user's self-help session, view information generated during that session, and/or execute certain actions with respect to the user's machine, all from the engineer's desktop. An active journal is maintained for each problem incident, and active journals may be used by other analysts to facilitate problem resolutions for new incidents.

Abstract: A cache controller is disclosed. The cache controller includes potential replacement list, a plurality of valid bits and a number of counters. The potential replacement list includes a number of entries. Each of the valid bits corresponds to one of the entries. Each of the counters also corresponds to the one of the entries.

Abstract: Disclosed is a method and apparatus for optimizing memory space and improving the write performance in a data processing system having a data volume with multiple virtual copies thereof. In one embodiment of the method, a first virtual copy of a primary data volume is created. Thereafter, first data of the primary data volume is modified. A second virtual copy of the primary data volume is created after modification of the first data thereof. A write-data transaction for modifying second data of the modified primary data volume is generated after creation of the second virtual copy. The second data of the modified primary data volume is copied to memory allocated to store data of the second virtual copy. The second data of the modified primary data volume is modified after the second data is copied to the memory allocated to store data of the second virtual copy.

Abstract: A network element receives frames from multiple ring networks. Each ring network linked to the network element is supported by a designated support program. The received frames are monitored for conditions indicative of a failure in one of the ring networks. Upon detection of a failure condition, the designated support program for the failing ring network is determined and notified. The designated support program then addresses the failure condition by, for example, switching to a backup link. In one example, the multiple ring networks are SONET BLSR networks.

Abstract: A method for restoring a virtual path, provisioned between a source and a target node, in a mesh zoned optical network is described. The method, in one embodiment, broadcasts or floods restore path requests in the network to expedite the identification of an alternate route and minimize the service disruption for failed virtual path. The flooding of requests is controlled to ensure efficient performance of the network yet guaranteeing minimum restoration time to allow critical telecommunication related traffic to flow through the network with virtually no interruption. The constant update of nodal topology by each node allows a fast identification of alternate physical path for failed virtual path.

Abstract: A general purpose, software-controlled central processor (CP) can be augmented by a set of task specific, specialized peripheral processors (PPs). The central processor accomplishes its functions with the support of the PPs. Peripheral processors may include but are not limited to a packet parser, a packet deconstructor, a search engine, and a packet editor. At each step in the use of this network processor system, the central processor has an opportunity to intervene and modify the handling of the packet based on its interpretation of PP results. The programmable nature of the CP and the PPs provides the system with flexibility and adaptability.

Abstract: A system allowing a target machine to be booted up from a disk image stored in memory. Instead of reading the boot-up information from a disk drive or other physical device the data is read from memory. No modification is necessary to native operating system, input/output subsystem, bootstrap code, etc., since the invention modifies characteristics, such as vectors used by the operating system, to make the disk image in memory appear to be the same as a standard external device.

Abstract: An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. An error insertion circuit is also provided for verifying correct operation of encoding and decoding circuits. A desired number of errors may be programmed for insertion into the OC-48 data signals. Error insertion may be performed in an iterative fashion to insert into different data signals the desired number of errors, wherein the errors are placed within the code words of the data signals at different location permutations for each data signal. In one implementation, error verification is performed using an error accumulator located in the receiver, and means are provided for examining an error accumulator count of the error accumulator to see if the number of accumulated errors matches with the number of inserted errors.

Abstract: A switching apparatus is disclosed that employs a relatively simple and inexpensive switching matrix, but which avoids interruption of existing connections when connections are added or removed. The switching matrix switches errorlessly by controlling the point in time at which switching occurs. Using such a technique, switching can be performed without disturbing the connections already configured in the switching matrix, and so is referred to herein as being non-blocking. Optionally, the incoming data can be rearranged to provide a larger window of time in which the switching matrix can be switched. In the case of a switch using an optical backplane, this also allows more time for various components of the system (e.g., clock/data recovery units) to re-acquire lock. The switching apparatus includes a switching matrix and control circuitry. The switching matrix has a matrix input, a control input and a number of matrix outputs, and is configured to receive an information stream at the matrix input.

Abstract: Devices capable of protecting electronic components during the occurrence of a disturbance event using printed circuit board manufacturing techniques. A three (3) layer structure is formed comprising a polymer-based formulation sandwiched between two electrode layers. The devices can be manufactured in panel form providing high quantities of devices which can be removed from the panel and applied directly to the component to be protected. Desired patterns can be formed on either one of the electrode layers by photo-etch techniques thereby providing a process that can be tailored to a large number of applications.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: The present invention defines a method and apparatus to extend class-based queuing (CBQ) with multiple “behavioral” queues per class, to include a dynamic weighting mechanism between these queues. The packets are forwarded from the behavioral queues according to the weighting assigned to each queue. The weighting for packet scheduling of the queues is adjusted to account for additional flow going through the queues. The weight of a queue is controlled relative to the weight available to other queues. When a flow is reclassified, the queue weights is readjusted accordingly. Well behaved flows experience low delay and can thus achieve a fair bandwidth allocation without having to have multiple packets queued to compete with non-adaptive aggressive flows.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: In one embodiment of the method, first and second data volumes are created. Thereafter, a first data portion of the first data volume is overwritten with a first data portion of the second data volume. A second data portion of the first data volume is overwritten with a second data portion of the second data volume. In one embodiment, the first and second data portions of the first data volume are overwritten with the first and second data portions of the second data volume, respectively, in response to a command to restore or synchronize the data contents of the first data volume to the data contents of the second data volume. A virtual point-in-time (PIT) copy of the first data volume is created after overwriting the first data portion but before overwriting the second data portion.

Abstract: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in a integrated circuit and forming electrically conductive interconnect lines after formation of the tungsten plugs, wherein at least one tungsten plug is electrically connected to at least one electrically conductive interconnect line. Separate from the formation of the tungsten plugs and electrically conductive interconnect lines, a gas is introduced into a liquid. At least one electrically conductive interconnect line is then contacted with the gas introduced liquid.

Abstract: A method and apparatus for centralized control of a network is described. The network includes a number of nodes. The method includes creating a database and storing the database on a master node of the network. The database contains topology information regarding a topology of the network. Each of the nodes is coupled to at least one other of the nodes, with the master node being one of the nodes.

Abstract: A method and apparatus for applying selective backpressure to control a multi-stage interconnection network (MIN). At one or more stages in the MIN, local information is used to define a queue status parameter for each local queue in the fabric. At the egress linecard, the upstream queue status parameter is periodically combined with the egress linecard's output queue status to generate a queue-specific backpressure signal. The backpressure signal continuously indicates to the ingress linecard that a specific fabric queue or queues is experiencing congestion and that the ingress linecard should therefore slow down or stop sending additional packets to the affected queue. Status computation mechanisms, which are state machines in one embodiment of the present invention, are incorporated in each switch element in at least the last stage of the switch fabric.