Abstract: An LDMOS transistor includes drift regions from the body to the drain and the source terminals and is capable of handling high voltages at both the source and drain terminals. In one embodiment, a transistor includes a body region formed in a first well, a conductive gate formed over a first dielectric layer where the first dielectric layer overlies the first well, a second dielectric layer encircling the first dielectric layer, a drain region abutting one edge of the second dielectric layer and a source region abutting an opposite edge of the second dielectric layer. A first drift region is formed between the source region and the body region while a second drift region is formed between the drain region and the body region. Accordingly, the drain and source region of the transistor is interchangeable. In one embodiment, the first and second dielectric layers are a contiguous field oxide layer.

Abstract: An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

Abstract: A current source includes a first circuit branch of a pair of diode-connected transistors with a resistor connected at the drain terminal and a second circuit branch of an inverter pair of transistors. Both of the circuit branches are supplied by a first current source powered by a supply voltage. The transistors are biased in the subthreshold region and have non-nominal size ratios. A first voltage and a second voltage are established across the resistor and the voltage difference causes a current proportional to absolute temperature to flow in the resistor. The second circuit branch functions as an error amplifier providing an “error signal” to facilitate voltage regulation. The regulation is realized in a third circuit branch which receives the “error signal” and draws excess current from the first current source so that the first voltage and the second voltage remain at the ideal regulated operation point.

Abstract: A structure and process are provided for using a single wire or data bus to detect collisions between two communication nodes connected by the single wire by sensing current changes in the wire, where large current changes indicate a collision. When a second node wants to obtain control of the wire on which a first node is transmitting data, the second node transmits a special data packet to ensure a collision and cause a large current to flow on the wire. Once a large current is detected in the wire to indicate a bit difference or collision, the first node stops transmitting and waits until it receives a synchronization bit pattern, which will indicate that the special data packet transmitted by the second node has ended. The two nodes are now synchronized, such that the second node has control of the wire and can begin transmission of a data packet. In order to indicate a collision, the large current flow must remain high after a specified time interval, such as a clock cycle.

Abstract: An LDMOS transistor includes a body region, a source region, a conductive gate, an alignment structure and a drain region. The conductive gate is insulated from the semiconductor layer by a dielectric layer and overlies the body region. The source region is formed in the body region and is formed self-aligned to a first edge of the conductive gate. The alignment structure is formed adjacent a second edge, opposite the first edge, of the conductive gate. The alignment structure has a first edge in proximity to the second edge of the conductive gate. The drain region is formed in the semiconductor layer self-aligned to the second edge, opposite the first edge, of the alignment structure. The alignment structure can be formed in a polysilicon layer or a dielectric layer. The incorporation of the alignment structure in the LDMOS transistor enables self-aligned drain region or drain contact opening to be formed.

Abstract: A circuit is provided to transfer data between a first data bus section operating on a first supply voltage and a second data bus section operating on a second, different supply voltage. The circuit includes a first circuit path and a second circuit path each coupled to receive a data signal from one data bus section and to drive the other data bus section. Each of the first and second circuit paths includes a delay circuit, a flip flop, a logic circuit providing an AND function and an output driver circuit. In operation, when the data signal received on one of the first and second data bus sections has a first logical value, an output driver signal of the respective circuit path is asserted and the output driver circuit drives the other data bus section to the first logical value in response to the output driver signal.

Abstract: A bipolar transistor includes an auxiliary diffusion region formed in the base region having a conductivity type opposite to the base region and being electrically coupled to the base region. Alternately, the auxiliary diffusion region can be formed in the collector region where the auxiliary diffusion region has a conductivity type opposite to the collector region and is electrically coupled to the collector region. The auxiliary diffusion region forms a secondary parasitic transistor in the bipolar transistor having the effect of suppressing parasitic bipolar conduction caused by a primary parasitic bipolar device associated with the bipolar transistor.

Abstract: An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

Abstract: A digital photoimaging device is presented. The digital photoimaging device includes a photosensor array having supporting circuitry formed on a second substrate produced, for example, with CMOS process technology and photosensors formed on a first substrate. The first substrate is processed separately from the second substrate so that the photosensors formed on the first substrate can be optimized while also optimizing the circuitry formed on the second substrate. The first substrate is then placed into electrical contact with the second substrate so that signals from the photosensors on the first substrate arc received by the supporting circuitry on the second substrate. In one embodiment, the supporting circuitry includes an array of support circuits each including an analog-to-digital converter.

Abstract: A circuit for sensing a voltage across a power switch includes a transmission gate, a low pass filter and a comparator. The power switch is controlled by a control signal for turning the power switch on and off to generate a switching voltage at a first current handling terminal of the power switch. The transmission gate is turned on whenever the power switch is turned on to sample the voltage across the power switch when the power switch is turned on. The sampled voltage is filtered by the low pass filter to remove high frequency transients. Finally, the comparator compares the filtered voltage to a reference voltage. The comparator provides an output signal having a first value when the filtered voltage is less than the reference voltage. The circuit can be used as a load sensing circuit to sense the load condition under which the power switch is being operated.

Abstract: A current sense amplifier circuit for detecting a first current includes an input gain stage incorporating a feedback loop, a current mirror, a charge integration stage and a comparator. The first current is coupled to an input node of the input gain stage where the input gain stage operates to maintain the voltage at the input node at a substantially constant level. The current mirror is coupled to mirror the first current into a second current. The charge integration stage is coupled to integrate charge associated with the second current to develop a first voltage. The comparator is coupled to compare the first voltage to a reference level and providing an output signal. The comparator generates an output signal having a first value when the first current exceeds a predetermined threshold level and a second value when the first current is less than the predetermined threshold level.

Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal coupled to receive a first reference signal having a number of levels, a second input terminal coupled to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexor coupling the multiple number of analog input signals to a multiple number of corresponding differential pairs. The multiplexor selects one of the multiple number of differential pairs based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: An image matching method for matching a first image and an overlapping second image includes generating a first set of working layers of the first image and a second set of working layers of the second image. The method determines an overlap between an initial working layer of the first image and an initial working layer of the second image where the initial working layers have a smaller pixel array size and a lower image resolution than the other working layers. The method selects a feature point in the working layer of the first image and determines a position in the working layer of the second image corresponding to the feature point. The method then determines the motion parameters based on the feature point and the position in the first and second images.

Abstract: A peak detector employs switched capacitor filtering to implement long time constant and variable attack and decay characteristics. In one embodiment, the peak detector includes a first switch, a rectifier, a first capacitor and a second switch in the attack path, and a third switch, a second capacitor and a fourth switch in the decay path. The peak detector further includes a third capacitor coupled to the attack and decay paths and having a capacitance greater than the capacitance of the first and second capacitors. In operation, the attack path is activated by alternately closing the first and second switches to sample the input signal and generate an output voltage at the third capacitor indicative of the peak voltage value of the input signal. The second circuit path is activated by alternately closing the third and fourth switches to decrease the output voltage at the third capacitor.

Abstract: A charge balancing modulation system for digitizing the output of a variable impedance sensor utilizes synchronous excitation of the input sensor and AC coupling of the analog input signal. The modulation system also implements correlated double sampling to provide low noise and highly accurate analog-to-digital conversions. In one embodiment, the modulation system includes an excitation source for providing a switched current to the input sensor and generating an input voltage step in response, and an integrator including an input capacitor, an amplifier and an accumulation capacitor. The input capacitor AC couples the analog input signal to the integrator. The integrator is controlled by switches operating in complementary state for enabling correlated double sampling operation or enabling data dependent charge accumulation operation. The modulation system generates an output data stream exhibiting a ones density proportional to the magnitude of the average input voltage step.

Abstract: A projection display system includes a light source emitting a randomly polarized light and a polarization recapture system including a tunnel integrator and a transmitting/reflecting polarizer coupled to the output end of the tunnel integrator. The input end of the tunnel integrator includes an input aperture and a reflective inside surface coated with a quarter wave retarder. In operation, the randomly polarized light enters the tunnel integrator through the input aperture. The polarization recapture system transmits light having a first polarization as polarized light output and recycles light having a second polarization orthogonal to the first polarization. The light having the second polarization is reflected by the transmitting/reflecting polarizer back into the tunnel integrator. The polarization recapture system recycles the light having the second polarization by reflecting and reorienting the light having the second polarization to light of the first polarization.

Abstract: A compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system includes a first capacitor, an amplifier with capacitive feedback and a second capacitor, connected in series between an input node and a summing node in the first circuit. In one embodiment, the summing node is an intermediate node between two gain stages of a second circuit in the first circuit. The capacitive feedback can be formed by a third capacitor coupled in parallel with one or more of the gain stages in the amplifier. In operation, the capacitance of the second capacitor and an input impedance of the second gain stage of the second circuit introduce a zero in the closed loop feedback system at the third node. The compensation circuit can be applied to a switching regulator controller for adding a zero in the feedback system of a switching regulator.

Abstract: A bootstrap reference circuit includes a shunt regulator for generating a reference voltage at a first node, a current source generating a current, and a current mirror coupling the current to the shunt regulator for supplying the shunt regulator. In operation, when the shunt regulator is powering up, the current has an increasing magnitude when a voltage at the first node is less than a predefined voltage value where the predefined voltage value is less than the reference voltage. Furthermore, the current has a decreasing magnitude when the voltage at the first node is greater than the predefined voltage value. In one embodiment, the shunt regulator includes a bandgap reference circuit and the predefined voltage value is less than the bandgap voltage of 1.24 volts.

Abstract: A method for measuring a temperature of an integrated circuit is disclosed. The integrated circuit includes a temperature sensing element being excited by a first switched current and a second switched current. The method includes coupling a first capacitor to the temperature sensing element through a first switch and coupling a second capacitor to the temperature sensing element through a second switch. The first and second capacitors are external to the integrated circuit. The method further includes charging the first capacitor through the first switch to a first voltage when the temperature sensing element is being excited by the first switched current, charging the second capacitor through the second switch to a second voltage when the temperature sensing element is being excited by the second switched current, and measuring a difference between the first voltage and the second voltage to determine the temperature of the integrated circuit.

Abstract: A method and apparatus for etching a semiconductor die are disclosed whereby flowing an etchant material across an inactive thereof thins the semiconductor die. In one embodiment, the etchant includes a mixture of nitric acid, hydrofluoric acid, and acetic acid and turbulently flows from one edge of the semiconductor die, across the inactive surface of the semiconductor die, to an opposing edge of the semiconductor die.