Abstract: An error amplifier circuit includes a differential amplifier with a cascode gain stage and an amplifier. The differential amplifier receives a first input signal and a second input signal and generates an output signal on an output terminal indicative of the difference between the first input signal and the second input signal. The cascode gain stage is coupled to receive the output signal of the differential amplifier and generates a second output signal. The cascode gain stage is biased by a bias current generated by a current mirror. The amplifier receives the second output signal from the cascode gain stage and generates a third output signal. The cascode gain stage is biased by a control signal for causing said current mirror to generate a bias current having substantially constant magnitude over variations in voltage differences of the first input signal and the second input signal.

Abstract: A toothbrush with removable brushing members includes a handle, a brush head extending from the handle, and a first brushing member of soft wood. The brush head includes a bottom surface and a body together defining a cavity for receiving the first brushing member. The brush head further includes an anchoring member extending partially around the inside perimeter of the body except at a first end of the inside perimeter of the body. The first brushing member is inserted into the cavity at the first end and is slid along the cavity into the anchoring member. The anchoring member compresses against and bites into the sides of the first brushing member to secure the first brushing member in the cavity. The toothbrush can include multiple brushing members. In one embodiment, the brushing members are stubs made of siwak sticks so that effective dental cleaning can be carried out using siwak.

Abstract: A diode-triggered NPN ESD protection device includes a P-Base region enclosing the emitter region of the NPN transistor for enhancing the reliability of the ESD protection device. The incorporation of the P-Base region encourages bulk transistor action and inhibits surface transistor action such that the reliability of the protection device is enhanced. In another aspect of the present invention, a trigger voltage control method is applied to a diode-triggered ESD protection device to extend the periphery length of the p-n junction of the trigger diode without increasing the size of the protection device. By extending the periphery length of the p-n junction, the trigger current generated by the trigger diode is increased so that the trigger voltage for the ESD protection device can be lowered, providing effective ESD protection. The periphery length is extended by using a shaped periphery, such as a corrugated periphery or a perforated periphery.

Abstract: A multi-channel bit-serial analog-to-digital converter with reduced channel circuitry is described herein in which a one-bit comparator circuit is split between a first part located within an input channel and a second part located outside the input channel. The external part of the comparator and the one-bit latch are shared by a plurality of input channels. In the preferred embodiment, a two-dimensional sensor array of pixel elements is fabricated in a single integrated circuit. Each of the pixel elements is an input channel which comprises a photodetector and the front-end part of the one-bit comparator. The external part of the comparator and the one-bit latch are formed in the periphery of the sensor array and are shared by a group of pixel elements, such as a column of pixel elements. In one embodiment, by connecting the output of an inverter to the control signal terminal of the comparator, the comparator can also be used as a buffer for analog readout.

Abstract: A rear screen projection system uses a single monochrome liquid crystal display (LCD) panel for displaying full color images. In one embodiment, an apparatus for projecting an image includes an illumination source generating polarized light beams in three different primary colors, a monochrome liquid crystal display panel including a two-dimensional array of addressable pixels, the array of addressable pixels is divided into multiple image areas, and a projection lens assembly for aligning and projecting the images generated by the multiple image areas of the liquid crystal display panel to form a full color image. In one embodiment, the illumination source includes a light source emitting randomly polarized white light, a polarizing element coupled to receive the randomly polarized white light and generate a polarized white light beam, and color separating elements for separating the polarized white light beam into the polarized light beams in three different primary colors.

Abstract: A semiconductor device includes a polysilicon layer in which a first region of a first conductivity type and a second region of a second conductivity type is formed. The first region and the second region form a p-n junction in the polysilicon layer. The semiconductor device further includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region. In operation, a low resistance path is formed between the first and second metallization region when a voltage or a current exceeding a predetermined threshold level is applied to the first or the second region. The voltage or current is applied for zap trimming of the p-n junction where the voltage or current exceeding a predetermined threshold level, together with the resulting current or resulting voltage, provides power sufficient to cause the low resistance path to be formed.

Abstract: A lateral DMOS transistor incorporates one or more enhancement schemes for improving the breakdown voltage characteristics and ruggedness of the transistor. In one embodiment, the drain region of the lateral DMOS transistor is separated from the body region by a first distance in the rectilinear region necessary to achieve a first breakdown voltage, and separated by a second distance in the curved region necessary to achieve at least the first breakdown voltage, the second distance being greater than the first distance. In another embodiment, the gate partially overlies the field oxide region by a third distance in the rectilinear region and by a fourth distance in the curved region, the fourth distance being greater than the third distance. The enhancement schemes optimize the breakdown voltage characteristics and ruggedness of the lateral DMOS transistor in both the rectilinear and curved regions.

Abstract: A semiconductor structure which protects against damages to an integrated circuit caused by electrostatic discharge (ESD) at a power supply pin includes a channel stop field plate coupled between a power supply terminal associated with the power supply pin and contacts to N-type substrate or N-wells formed in the semiconductor structure receiving the power supply voltage. The field plate functions to inhibit surface leakage current and is also used to introduce a resistance between the power supply pin and connections to N-wells or the N-substrate, thereby providing protection to the wells or substrate against damages caused by an ESD event. By exploiting an existing structure used in typical integrated circuit for ESD protection, ESD immunity of a semiconductor device can be enhanced without consuming additional silicon area.

Abstract: A system and method for performing frequency compensation in a video digital cameral utilizing a time-indexed multiple sampling technique is presented. The frequency compensation removes distortion from the digital image signal captured by the video digital camera as compared with a human-perceived image signal.

Abstract: A system on a chip for an image sensor includes a sensor array, a readout circuit, a data memory and a processor. The sensor array includes a two-dimensional array of pixel elements and a plurality of analog-to-digital conversion (ADC) circuits where each ADC circuit is coupled to one or more pixel elements in the sensor array. The readout circuit is coupled for reading the pixel data from the sensor array. The data memory is coupled for the sensor array for storing the pixel data. The processor is coupled for processing the pixel data. In operation, the system on a chip deactivates at least one noise-inducing circuit while a noise-sensitive circuit is activated. In one embodiment, the noise-sensitive circuit is one or more of the ADC circuits, and the noise-inducing circuit is one of the readout circuit, the data memory and the processor.

Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: A system and method for performing low-power analog-to-digital conversion in digital imaging system utilizing a time-indexed multiple sampling technique is presented. The analog-to-digital converter is switched off when the digital image signal resulting from an exposure time selected from a plurality of exposure times satisfies a threshold value.

Abstract: A digital image sensor includes a sensor array of digital pixels which output digital signals as pixel data. Each of the digital pixels includes a photodetector producing an analog signal indicative of the amount of light impinging on the sensor array and a charge transfer amplifier coupled to receive the analog signal and generate an amplified pixel voltage signal. The digital image sensor further includes analog-to-digital conversion (ADC) circuits located within the sensor array. Each of the ADC circuits is connected to one or more charge transfer amplifiers of the digital pixels for converting the amplified pixel voltage signal of each digital pixel to a digitized pixel voltage signal. The charge transfer amplifier operates to increase the sensitivity of the digital image sensor. The charge transfer amplifier can be implemented as a transfer gate with a floating diffusion as a measuring capacitor.

Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.

Abstract: A control circuitry for conveying video data in a flat panel display transmits video data using reduced swing differential signals that are time-multiplexed on a data bus. Data transmission schemes are provided to reduce data transitions on the data bus. A repeat last pixel scheme is used whenever the pixel data repeat horizontally on a display. A repeat last line pixel scheme is used whenever the pixel data repeat vertically on a display. A repeat last different pixel scheme is used whenever video data comprises mainly of monochrome information. In the alternate, a dynamic color pallet is used to store a few most frequently used pixel colors. When the current pixel color matches one of the colors stored, a pixel color address is transmitted instead of the pixel data itself. The use of reduced swing differential signaling on a time-multiplexed data bus together with one or more of the data transmission schemes achieves significant reduction in power consumption and electromagnetic interference generation.

Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: A driver circuit for alternately driving a first transistor and a second transistor connected in series includes primary and secondary anti-shoot-through protection. The driver circuit prevents shoot-through at the first and second transistors by using a pair of switch lock-out signals. The switch lock-out signals prevent one transistor from turning on until the other transistor is turned off. The driver circuit eliminates shoot-through in the driver devices driving the first and second transistors by using a pair of driver lock-out signals. The driver devices are turned on only briefly during the transitions of the first and second transistors. Otherwise, the driver devices are turned off. The driver lock-out signals ensure that no contention occurs between the driver devices and furthermore, set up the driver devices for the next On-Off switching sequence. The driver circuit can achieve a fast switching operation as well as improve the efficiency of the power transistors.

Abstract: A compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system includes a first capacitor, an amplifier and a second capacitor, connected in series between a feedback terminal and an input node of the first circuit. A first resistor is coupled between the feedback terminal and the input node to provide a resistive load to the compensation circuit. The amplifier amplifies the capacitance of the second capacitor to introduce a zero in the first circuit having effectiveness over a wide frequency range. In one embodiment, the compensation circuit is applied to a switching regulator controller for adding an effective zero in the feedback system of a switching regulator for compensating a double-pole introduced by a LC filter circuit in the switching regulator feedback system.

Abstract: A reference-corrected ratiometric current sensing circuit for sensing a current flowing through a load and a power-controlling pass device includes a sense device, a sense resistor, and a variable reference current source for providing a varying reference current. The varying reference current is varied according to a ratio of the voltage across the sense device to the voltage across the pass device. The ratiometric current sensing circuit of the present invention is capable of accurate current sensing in spite of disparities that may occur between the voltages across the sense and the pass devices. In one embodiment, the variable reference source includes a transconductance amplifier circuit that provides an output current indicative of the voltage difference at its input terminals. Furthermore, the variable reference current source includes a translinear circuit that works with the transconductance amplifier circuit to implement the prescribed arithmetic operations to generate the varying reference current.

Abstract: A voltage monitor circuit for monitoring a first voltage includes a switch and a comparator. The switch has a first position and a second position. When the switch is in the first position, the switch connects the comparator to a first voltage terminal to monitor a second voltage. When the switch is in the second position, the switch connects the comparator to a second voltage terminal to monitor a third voltage. The second and third voltages are scaled voltages of the first voltage to be monitored. The comparator provides an output signal indicating a status of the first voltage, that is, whether the first voltage is within an operative range. The voltage monitor circuit may further include a voltage divider connected between the first voltage and a ground potential. The voltage monitor circuit of the present invention can be incorporated in an electrical system for monitoring a battery voltage.