Abstract: An improved cell circuit for data readout with reduced number of read wordlines is provided in a memory block of a multiport memory array. The number of read wordlines is significantly reduced by using a decoder between the read wordlines and a multiplexer in the cell circuit. The memory block has a plurality of address inputs and stores a plurality of write data signals. In the cell circuit, the decoder receives as decoder inputs a subset of the address inputs and outputs a plurality of select signals. The multiplexer is coupled to the decoder to receive the select signals and select one of the write data signals based on the select signals. Additionally, the read wordlines are coupled to the decoder for carrying the subset of the address inputs to the decoder.

Abstract: A method for providing wireless communications system providers to adjust when soft and hard handoffs occur relative to the signal strengths of surrounding antennae. This is achieved by providing two sets of parameters. The first set of parameters is used to adjust either hard or soft handoffs, and the second set of parameters are added as an offset to the first set of parameters to adjust the other handoff, thereby, allowing the wireless communications system providers system to adjust soft and hard handoffs independently.

Abstract: Several local clock buffers are disclosed, each including an input section and an output section. The input sections are substantially identical, and include control logic and gating logic. The control logic produces a gating signal dependent upon multiple control signals and a time-delayed global clock signal. The gating logic produces an intermediate clock signal dependent upon the global clock signal and the gating signal. The output section produces at least one local clock signal dependent upon the intermediate clock signal. In one embodiment, the output section produces a first local clock signal dependent upon the intermediate clock signal and a second local clock signal dependent upon the first local clock signal. In another embodiment, the gating logic produces the intermediate clock signal dependent upon the global clock and gating signals and a feedback signal. The output section produces the feedback signal and one or more local clock signals.

Abstract: A bus architecture is provided to facilitate communication between independent bus masters and independent bus slaves by having two or more bus arbiters in a system-on-chip (SOC) system. Each bus master in the system is coupled to all bus arbiters in the system, so that each bus master can access a corresponding bus slave concurrently as well as sequentially. Such concurrent communication carries not only read and/or write data but also a target address of the corresponding bus slave, thereby enabling true concurrency in data communication between bus masters and bus slaves.

Abstract: The present invention provides a method and an apparatus for generating a phase error signal from a reference signal and a feedback signal using a modified reset generation mechanism. An input circuit receives a reference signal and a feedback signal. A phase error detector circuit generates a phase error signal based on the reference signal and feedback signal. The input circuit is reset and, after a delay, the phase error detector circuit is reset. The delay is selected so that there is no jitter associated with the dead zone.

Abstract: A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

Abstract: A method and an apparatus for suppressing errors reported by an error check function of a circuit. The method and apparatus utilizes a shifter to provide an enablement bit for the error reporting. An error is reported only if the enablement bit is set such that it allows the error to be latched through the circuit.

Abstract: The invention includes a circuit for aligning the phase of a clock derived from a frequency multiplied version of a reference clock used in a computer system. The dynamic phase alignment circuit includes a few logic gates to perform the operation of delaying the derived clock, detecting its phase misalignment, and correcting such misalignment by incrementally aligning the phase of the derived clock to the reference clock. The invention is capable of aligning the phase of a derived clock to a reference clock in a computer system whose CPU operates at as high a frequency as about 500 MHz or higher.

Abstract: A first multiple-lens array designed with positive-power lenses produces multiple bundles of converging light rays, and a second multiple-lens array designed with negative-power lenses produces multiple bundles of collimated light rays at a certain optimal separation between the two multiple-lens arrays. As the axial separation between the two multiple-lens arrays increases, the divergence of the entire beam of light increases.

Abstract: An apparatus and method for passing messages through a bus-to-bus bridge while maintaining ordering. The method comprises passing messages into a message container in the bus bridge without using the bridge buffer, setting a flag that tracks all the writes in the write queue ahead of when the message was put into the message container, blocking the receiving device on the bus connected to the bridge from accessing the message container until the flag is cleared, and clearing the flag when all the writes put into the write queue ahead of when the flag was set have been written to local memory on the receiving bus, then allowing the device on the receiving bus that is the intended recipient to receive the message.

Abstract: A stage lighting instrument having a high-intensity light source or lamp coupled with a concave reflector, and a projection optical system having a lens system that includes an aperture stop. The lens system forms a real image of the light source encompassing or near the aperture. A color filter and dimming system may be located within the lens system so that the color filter and dimming elements occupy a volume of space near the aperture stop and within the real image of the light source. By locating the color and dimming apparatus near the aperture stop and within the volume occupied by a real image of the light source, superior color mixing, dimming and integration is achieved using simple, un-patterned filters and a simply-shaped dimmer panel. A color filter and dimming system may alternatively be located as close to the light source as possible so that a real image of the color filter and dimming elements is formed near the aperture stop where the image of the light source is formed.

Abstract: A virtual synchrony wide area network (100) which has at least a first local area network (LAN) (110) and a second LAN (120). A first router (114) and a second router (116) are connected to the first LAN (110), and a third router (142) and a fourth router (146) are connected to the second LAN (120). A point-to-point link (152) is connected between the first and third routers, (154) between the first and fourth routers, (156) between the second and third routers, and (158) between the second and fourth routers. Each router is provided with computer program code (206) for controlling the flow of messages through the routers and to maintain local total order with minimal latency.

Abstract: A method of analyzing timing reports in a microprocessor design for quick identification of all negative timing paths has been provided. Timing paths are first grouped and saved in a list file. A timing analysis program searches the timing report file for timing paths that match those in the list file. Summary reports have been generated for the existing timing paths. If there are new timing paths, summary reports for the new timing paths are generated. The new timing paths go through the same procedure until all negative timing paths are identified.

Abstract: A method is disclosed for redirecting calls more efficiently, whereby an LDAP query is encoded with a called telephone number. The LDAP query is transmitted from a TCP/IP to an LDAP server via an IP network, and the TCP/IP awaits a response back from the LDAP server, which response identifies a corrected destination address, and may include translated digits which may be used in telephony routing.

Abstract: An encoder for compressing data is described, including a history buffer having multiple storage locations for storing target data units. The encoder is configured to input a target data string including multiple target data units, and additional data (e.g., security data associated with the target data string). In the event the history buffer contains multiple matching strings that match the target data string, the encoder is configured to select a displacement value of one of the matching strings dependent on a portion of the additional data, and to produce a copy pointer corresponding to the target data string and including the selected displacement. The selected displacement value in the copy pointer conveys the portion of the additional data. A decoder for decompressing data is also described, including a history buffer having multiple storage locations for storing data units.

Abstract: A high intensity light projector for stage, architectural and similar applications includes a controllable image quality projection gate providing advanced visual effects. The projection gate, capable of selectively scattering or transmitting incident light, may be constructed of an array of scattering liquid crystal material in combination with infrared and ultraviolet reduction means which provide in the high intensity beam, a stable thermal environment by minimizing the absorption of light by the projection gate. Additional thermal efficiency is provided by supplemental cooling means. Color control is also provided in the form of dichroic filter wheels forming cooperating adjustable low, high and band width filters including saturation control. A color measuring feedback sensor is also provided. An intensity measuring feedback sensor controls a spatially-modulated, variable-density, reflectively-coated dimming wheel. A programmable gobo system has provisions for gobo selection, orientation, and rotation.

Abstract: A communications architecture for enabling IP-based mobile communications includes a Local Service Function (LSF) component configured to serve as an IP-based serving area network for a set of x-Access Networks, and a Network Service Function (NSF) component configured to serve as an IP-based home network by managing a MN's subscription and associated profile so that the MN is authorized to use the resources of the LSF. An x-Access Network (xAN) is interconnected to the LSF and NSF for providing heterogeneous Layer 2 access for MNs irrespective of access technology.

Abstract: A method for providing a memory scheme in computer architectures in an efficient and cost effective manner. A processor is configured with access to dual-L2 caches, preferably configured to cache program instructions and data in one cache and shared data in another cache. In one embodiment of the present invention, one L2 cache is accessible to networking interface devices. Optionally, the cache accessible by the networking interface devices is configured as networking buffers, providing cache for packet data being sent within a network. By use of this invention, the packet forwarding speeds in a conventional computer architecture may be increased.

Abstract: Disclosed is an apparatus for and method of routing telephony data packets by checking the address of each data packet as the data packet is sent to a common random access memory to be used by all of a plurality of router. The appropriate output link is ascertained by use of a lookup table accessible by each of the plurality of routers. The location of the data packet in memory is then sent to a FIFO entity associated with the appropriate output link. When the queue for that link reaches a pointer in the FIFO for that data packet, it is retrieved from memory and forwarded to its destination.

Abstract: A latching dynamic logic structure is disclosed including a static logic interface, a dynamic logic gate, and a static latch. The static logic interface receives a data signal, a select signal, and a clock signal, and produces a first intermediate signal such that when the select signal is active, the first intermediate signal is dependent upon the data signal for a period of time following a clock signal transition. The dynamic logic gate discharges a dynamic node following the clock signal transition dependent upon the first intermediate signal. The static latch produces an output signal assuming one of two logic levels following the clock signal transition, and assuming the other logic level in the event the dynamic node is discharged. A scan-testing-enabled version of the latching dynamic logic structure is described, as is an integrated circuit including the latching dynamic logic structure.