Abstract: A local clock signal generation system is disclosed including multiple local clock buffers each receiving a global clock signal and producing a version of one or more local clock signals derived from the global clock signal. Each local clock buffer includes an input section and an output section. The input sections are substantially identical such that timing differences between the versions of the one or more local clock signals are reduced. An electronic circuit is described including the local clock signal generation system and a latch (e.g., a master latch of a flip-flop). A local clock buffer produces a gating signal and a local clock signal received by the latch. When the gating signal is a certain logic value, the local clock signal is a steady logic value, and the latch produces an input data signal as an output signal. An integrated circuit including the electronic circuit is disclosed.

Abstract: A clock signal selector circuit is disclosed including a synchronizer circuit, two switching circuits, and a multiplexer. The synchronizer circuit synchronizes a first control signal to a first clock signal, thereby producing a second control signal. A first switching circuit produces the first clock signal at a first node when the second control signal is asserted. The multiplexer drives a second node with a signal at the first node when the second control signal is asserted. The second switching circuit forms an electrical connection between the first and second nodes when the second control signal is deasserted. The two switching circuits significantly reduce a probability of error at the second node due to metastability when the second control signal transitions from asserted to deasserted and the first clock signal is deselected. The second switching circuit provides electrical feedback from the second node to the first node.

Abstract: A system, method, and computer program product are provided for generating display data. The data processing system loads coefficient values corresponding to a behavior of a selected function in pre-defined ranges of input data. The data processing system then determines, responsive to items of input data, the range of input data in which the selected function is to be estimated. The data processing system then selects, through the use of a vector permute function, the coefficient values, and evaluates an index function at the each of the items of input data. It then estimates the value of the selected function through parallel mathematical operations on the items of input data, the selected coefficient values, and the values of the index function, and, responsive to the one or more values of the selected function, generates display data.

Abstract: A Resistor bank has first and second supporting member. Held on to the supporting members is a resistor element comprising a strip of resistor material which is bent into a zigzag shape. The strip is continuous and has a non-planar cross section profile. A plurality of insulating spacers mounted end to end on each of the first and second supporting members isolate the element from the first and second supporting members. The engaging surfaces of adjacent spacers are of a complimentary shape thereby to enable each spacer to move relative to each adjacent spacer with any flexing of the relevant one of the supporting members. The element is held by a plurality of clips each at a bend thereof on to a respective one of the supporting members. Each clip has at least one fastening lug for insertion into at least one fastening hole in a corresponding bend in the element.

Abstract: A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common software prefetch access patterns, by mapping the software prefetches to hardware, improved prefetching can be achieved without the need for additional hardware.

Abstract: A method and an apparatus are provided for implementing a logic circuit with integrated logic and latch design. A clock input is provided to the logic circuit. One or more static signal inputs are further provided to the logic circuit. One or more dynamic signal inputs are generated by dynamically gating the one or more static signal inputs with the clock signal. The one or more dynamic signal inputs are applied to the logic circuit, and one or more dynamic signal outputs of the logic circuit are generated. The one or more dynamic signal outputs are precharged, and the one or more dynamic signal outputs are evaluated. The one or more dynamic signal outputs are held when the one or more dynamic signal outputs are neither being precharged nor being evaluated. The one or more dynamic signal outputs are converted into one or more static signal outputs.

Abstract: A method for optimizing power management in the transmittal of a variable rate data transfer between two wireless stations, such as a Base Station Transceiver and a Mobile Station. This is achieved by determining the initial power and the initial signal-to-noise values based on the reliability of the transmission, the desired data transfer rate, the power required to transmit a fixed rate message, and the frame error rates. By the use of this invention, the capacity of a desired system and/or quality of a service provided by a desired system may be enhanced.

Abstract: A method, an apparatus, and a computer program are provided to reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line. The true node of the SRAM cell is evaluated through use of a floating voltage coupled to the true node of the SRAM cell. If the floating voltage stays substantially constant, the value read from the SRAM cell is a high. If the floating voltage is drained to ground, the value read from the SRAM cell is a low.

Abstract: Disclosed is an apparatus for and a method of overcoming signal delay problems in a read-out path occurring in connection with pipelined memory circuits. A latch type sense amplifier (SA) is used to receive the memory cell logic levels during a pre-charge state in a cycle prior to read-out. Thus, the SA may quickly provide an output signal during a read latch clock cycle. The SA output is passed through a dynamically enabled logic circuit to a latch circuit for holding the receiving logic value for use in the next clock cycle.

Abstract: A method and an apparatus for sharing a request queue between two or more destinations. The method and apparatus utilizes a common data table and a common age queue. The age queue is used to select the oldest request. The corresponding request from the common data table is then extracted and sent to the appropriate destination.

Abstract: A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the width of the input clock cycle, that is asserted one or two input clock cycles prior to the rising edge alignment of the input and output clocks, that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.

Abstract: A decoder for use in wordline/bitline redundancy control is disclosed. In one aspect, the decoder includes first and second wordlines respectively coupled to redundant first and second wordlines, where the first and second wordlines are configured to be activated based on decoded first and second addresses. In addition, the decoder includes first and second shift registers respectively coupled to the redundant first and second wordlines, where each is configured to respectively activate the redundant first and second wordlines when the first or second wordlines contain a defect. In addition, a method of selecting wordlines for use in wordline/bitline redundancy control and a wordline decoder having redundancy control capabilities are also disclosed.

Abstract: The present invention provides an integrated circuit VLSI temperature system for the calibration of threshold temperatures. A temperature sensitive ring oscillator (TSRO) generates a TSRO calibration parameter. A memory is employable to store the TSRO calibration parameter. A module is employable to determine a threshold TSRO oscillation frequency from the TSRO calibration parameter. A memory is employable for storing at least one threshold TSRO oscillation frequency.

Abstract: Disclosed is an apparatus for generating two constant width and symmetrical drive signals from two separate, but complementary, pulse width modulated control signals while also generating two pulse width modulated drive signals corresponding to said pulse width modulated control signals. The constant width drive signals are generated through the use of a toggle or latch set/reset circuit actuated by a given characteristic of each of the control signals.

Abstract: The present invention provides for a balanced laminated integrated circuit package. The package includes a two metal layer bumped circuit, a first adhesive layer having a thickness on a first side of the bumped circuit, a first outer conductive layer having a thickness bonded to the first adhesive layer and a second adhesive layer having a thickness substantially equal to the thickness of the first adhesive layer on a second side of the bumped circuit. The invention also includes a second outer conductive layer bonded to the second adhesive layer, the second outer conductive layer having a thickness substantially equal to the thickness of the first outer conductive layer.

Abstract: The present invention provides for a method of interconnecting a bumped circuit having relatively fine traces to an overlying conductive layer of a laminated circuit assembly. The overlying conductive layer is laminated with a suitable insulating adhesive over a bumped relatively fine pitch circuit layer. In the general vicinity of the desired power connection, a window substantially larger than the width of the bump is etched away from the conductive material of the trace of the outer conductive layer and the adhesive is plasma etched to expose the elevated portion of the desired bump of the bumped circuit. A conductive media such as conductive polymer or solder is then applied at the etched window of the overlying relatively coarse trace, which ensures an electrical connection between the exposed portion of the bump and the overlying trace.

Abstract: The present invention provides a subarray control apparatus and method. The subarray control includes a wordline driver configured to generate a wordline activation signal, and a write/read control signal generator configured to generate a write/read enable signal. In addition, the subarray control includes a timing generator configured to generate a wordline timing signal input to the wordline driver and a write/read timing signal input to the write/read control signal generator. The wordline activation signal is based on enable data captured by a first transparent latching circuit and the wordline timing signal generated within the subarray. The write/read enable signal is based on enable data captured by a second transparent latching circuit and the write/read timing signal generated within the subarray. Accessing subarray cells in a memory module and a memory module incorporating the subarray control are also disclosed.

Abstract: A laminated plate assembly in which the laminations in a stack are secured together by means of one or more interlocks or tabs that project from the uppermost lamination in the assembly through holes or slots in all the other laminations in the assembly, or around the periphery of the other laminations in the assembly, with each tab being bent or pressed against the underside of the bottom lamination in the assembly. This secures all the laminations in the stack together, much like a staple secures papers in a stack together, allowing for additional handling and processing of the laminated plate assembly without concern that the laminated plates in the stack will become misaligned or even become removed from the stack.

Abstract: Disclosed is an apparatus and method for decreasing the timing delay variation of output signals obtained from an SOI technology sense amplifier. The cross-coupled latch includes FETs where the body is connected to one of source and drain to minimize switching history effects while the input FETs have a higher than normal gate switching voltage to increase input signal sensitivity.

Abstract: A determination whether a network is connected to the Internet is made by configuring a first computer in the network to periodically generate a heartbeat message to a second computer outside the network. The second computer determines whether the heartbeat message is received, the receipt of which heartbeat message is indicative that the network is connected to the Internet.