Abstract: A data storage device includes a solid state data storage medium, a set of related data blocks and a controller. The set of related data blocks are non-contiguously stored on the data storage medium and have an original write sequence. The controller, responsive to a defragmentation request, maps the physical block addresses of the set of related data blocks to contiguous logical block addresses in the original write sequence while maintaining the non-contiguous physical block addresses of the set of related data blocks on the data storage medium.

Abstract: In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The circuit device further includes a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. The spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape.

Abstract: In a particular embodiment, a multi-path bridge circuit includes a backplane input/output (I/O) interface to couple to a local backplane having at least one communication path to a processing node and includes at least one host interface adapted to couple to a corresponding at least one processor. The multi-path bridge circuit further includes logic adapted to identify two or more communication paths through the backplane interface to a destination memory, to divide a data block stored at a source memory into data block portions, and to transfer the data block portions in parallel from the source memory to the destination node via the identified two or more communication paths.

Abstract: In a particular embodiment, a system to present search results is disclosed that includes a search system to retrieve search results from multiple data sources and to extract data from the search results. The system also includes a visualization system to generate a graphical user interface (GUI) including a visualization of data related to the search results and including multiple control options. The multiple control options include a first option and a second option related to the extracted data, where the first option is accessible to alter the visualization.

Abstract: An integrated circuit includes USB communication circuitry for communicating via a USB interface. The USB transceiver circuitry transmits data to and from the integrated circuit over the USB interface. The USB transceiver circuitry further provides protection to internal circuitry of the integrated circuit from a 5 volt short circuit on the USB interface.

Abstract: In an embodiment, a dot-product unit to perform single-precision floating-point product and addition operations is disclosed that includes a first multiplier tree unit adapted to multiply first and second significand operands to produce a first set of two partial products. The dot-product unit further includes a second multiplier tree unit adapted to multiply third and fourth significand operands to produce a second set of two partial products, a shared exponent compare unit adapted to compare exponents of the first, second, third and fourth operands to produce an alignment shift value, and an alignment unit adapted to shift the second set of two partial products based on the alignment shift value. The dot-product unit also includes an adder unit adapted to add or subtract the first set of two partial products and the second shifted set of two partial products to produce a dot-product value that is a single-precision floating-point value.

Abstract: In a particular embodiment, a method is disclosed that includes receiving first and second operands at a floating-point fused add-subtract circuit. The method further includes simultaneously performing add and subtract operations on the first and second operands via the floating-point fused add-subtract circuit to produce a sum result output and a difference result output. The floating-point fused add-subtract circuit includes sign logic, exponent adjustment logic, and shift logic that are shared by an add/round and post-normalize circuit and a subtract/round and post-normalize circuit to produce the sum and difference result outputs.

Abstract: In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.

Abstract: In a particular embodiment, a circuit device includes a first circuit having a first plurality of serial terminals including a first data receive terminal and a first data transmit terminal. The first plurality of serial terminals is communicatively coupled to a particular circuit via isolation circuitry to communicate first serial data. The circuit device further includes a second circuit having a second plurality of serial terminals including a second data receive terminal coupled to the first data transmit terminal and including a second data transmit terminal coupled to the first data receive terminal to communicate second serial data to the particular circuit via the first data receive and transmit terminals.

Abstract: A storage device with hardened security features has a storage medium, an interface, and a controller. The interface is adapted to communicatively couple the storage device to a host system. The controller is within the storage device and is adapted to read and to write information to and from the storage medium. The controller is adapted to require a security partition authorization from a manufacturer of the storage device before executing a security partition creation command received over the interface.

Abstract: Devices, methods, and systems of a communications channel detector are disclosed that can compare a plurality of candidate sequences of bits and decisions to identify unlikely error events. The detector may then discard at least one candidate sequence based on an unlikely error event to produce a set of remaining paths. A branch metric calculator may be adapted to calculate metrics for a set of remaining paths.