Abstract: A power factor correction circuit in which an inductor current is detected separately as a charging current indication signal and a discharging current indication signal by using a current sense resistor and a current sense circuit. A scaled-down output DC voltage is compared with a predetermined reference DC voltage by using an error amplifier which serves to produce an output voltage error signal. The output voltage error signal is then multiplied with a divided-down rectified input line voltage through the use of the multiplier to generate a sinusoidal reference signal. The sinusoidal reference signal is used by peak and valley comparators which also receive the charging and the discharging current indication signals. The outputs from the peak and the valley comparators are used to control a FET transistor which controls the input line current. As a result, the power factor correction circuit is capable of effectively eliminating a dead time and thereby achieving a near unity power factor.

Abstract: A switching circuit for outputting input and output signals from a single terminal includes an I/O signal interface circuit for forming a current path in parallel with a switch when a voltage at both terminals of the switch changes from high state to low state and for opening the current path when receiving a delay signal. An I/O signal separator provides the delay signal of predetermined time width when forming the current path to the I/O signal interface circuit and for blocking the current path during the delay period. Repeated and consecutive striking of a singular switch is ignored since only the first strike is effective. In addition, a display connected to a previously pressed switch remains continuously lighted when an interval between two consecutive struck different switches is shorter than the delay period.

Abstract: A binary counter or binary-coded-arithmetic counter uses local look-ahead to speed up ripple carry propagation. A succession of counter stages therein can be identified by respective consecutive ordinal numbers assigned in accordance with the order of carry propagation. Each counter stage receives a respective carry input and supplies a respective output signal, and each counter stage identified by even number supplies a respective complemented output signal. Each counter stage identified by odd number has a respective carry generation circuit for supplying a respective carry output signal which includes a NAND gate responsive to carry input to that counter stage and responsive to output signal from that counter stage, carry input for the next counter stage being supplied in response to the NAND gate response.

Abstract: A method for manufacturing a semiconductor device, e.g.

Abstract: A semiconductor device includes a metal wiring layer having a plurality of parallel, actual metal lines, with an endmost one of the actual metal lines being disposed adjacent a wiring-free region. The actual metal lines are electrically connected to an active circuit portion of the semiconductor device. At least one dummy metal line is interposed between the endmost one of the actual metal lines and the wiring-free region, with the at least one dummy metal line being disconnected from the active circuit portion. The dummy metal line(s) serve to prevent corrosion of the actual metal lines when the metal wiring layer is patterned by an etching process.

Abstract: An NTSC television signal transmitter also transmits through the same transmission channel a suppressed data carrier having a frequency differing from that of video carrier, having a symbol rate that is a multiple of horizontal scanning rate of video signal, having data frames occurring at a data frame rate that is the same as the video frame rate, and transmitting the symbols transmitted in each of alternate data frames in opposite phase during the next data frame. The data carrier has no image on the other side of the video carrier and preferably its modulation spectrum overlaps the video carrier. A receiver recovers data from such a data carrier buried in an NTSC television signal, using frame-comb filtering to separate data from interfering video signal.

Abstract: A method for manufacturing an electrode, e.g., a gate electrode of a MOS transistor, and an electrode and MOS transistor manufactured in accordance with this method. The method includes the steps of forming a first diffusion preventing layer on an underlying layer, forming a mask pattern having an opening on the first diffusion preventing layer, forming a metal layer on a portion of the first diffusion preventing layer exposed by the opening in the mask pattern, forming a metal layer on the exposed portion of the first diffusion preventing layer, forming a second diffusion preventing layer on the resultant structure, etching back the second diffusion preventing layer to leave a remaining portion thereof on the metal layer, removing the mask pattern, and forming a third diffusion preventing layer on exposed portions of the remaining portion of the second diffusion preventing layer, exposed sidewalls of the metal layer, and exposed portions of the first diffusion preventing layer.

Abstract: A stereo and dual audio signal identifying circuit including an FM detector receiving a second intermediate frequency signal, a bandpass filter, an AM detector. The circuit further including an amplifier having a first input receiving an output signal from the AM detector, and a second input receiving a signal derived from a series connected resistor and DC-filtering capacitor connected between the second input and ground, and having a feedback resistor connected between the second amplifier input and the amplifier. The amplifier drives a second stage of the circuit including a voltage controlled oscillator, a phase detector and a low-pass filter. The particular disposition of the DC-filtering capacitor within the circuit allows the capacitor to be externally connected to a single pin in an IC package incorporating the circuit.

Abstract: A circuit which controls a self-refresh period of a semiconductor memory device includes a pulse generating circuit which outputs a periodic pulse train in response to an external control signal, a frequency-dividing circuit which outputs a plurality of pulse trains having different respective periods by frequency-dividing the pulse train, at least one temperature detector which detects an ambient temperature of the memory device and outputs a temperature detection signal when the ambient temperature exceeds a predetermined threshold level, at least one voltage detecting circuit which detects a power supply voltage applied to the memory device and outputs a voltage detection signal when the power supply voltage reaches a predetermined level, a combination pulse train generating circuit which outputs a plurality of combination pulse trains by variously combining the plurality of pulse trains output by the frequency-dividing circuit, and a pulse selecting circuit which outputs a self-refresh master clock by sel

Abstract: A method of manufacturing and a structure of a semiconductor device is disclosed whereby a gate insulating layer, a polycrystalline silicon layer, a tungsten silicide layer and a first insulating layer are formed on a semiconductor substrate. Gates are formed by the removal of the layers by dry etching, wherein the etch rate of the tungsten silicide layer is faster than the other layers, thereby forming an undercut region in the tungsten silicide layer. A second insulating layer is formed on the surface of the resultant structure to form spacers, and a contact window is formed between the gates via an etching process. The second insulating layer portion which forms the spacers need not be thick to prevent etching of the gates when forming the contact window, therefore good step coverage is achieved and reliability of the device is increased.

Abstract: An infinite-distance detecting circuit for use in an auto-focusing system in a camera including an amplifier section for amplifying a position detection signal, a reference signal generation section sampling the position detection signal, holding the sample as a reference signal level, and amplifying the reference signal level in accordance with a variable gain in order to generate the infinite-distance-determining reference signal, and a comparator comparing the infinite-distance-determining reference signal to the amplified position detection signal in order to detect an infinite focus distance.

Abstract: A method of arranging column decoders in a video RAM, including the steps of arranging a memory cell array into a plurality of memory sub-cell arrays, and positioning a column decoder to one side of each memory sub-cell array between the memory sub-cell array and centrally located peripheral circuits including a predecoder. The column decoder includes a RAM column decoder section and a SAM column decoder section.

Abstract: A decoding circuit and method for a semiconductor memory device simplifies a decoding process by individually performing a large block decoding and small block decoding operations, and thereby reduces the total time delay taken in an address decoding process and layout area occupied by decoding circuits. The decoding circuit for a semiconductor memory device having a memory cell array including a plurality of large blocks, each large block including m small blocks (wherein m=2,3, . . . ) and having a plurality of memory cells being arranged in a matrix form, and a plurality of reading/writing circuits each corresponding to said large blocks, includes a first decoding circuit for receiving a first address to simultaneously select respective specific small block in each of the large blocks, corresponding to the first address, and a second decoding circuit for receiving a second address to enable a selected one of the reading/writing circuits corresponding to said second address.

Abstract: A semiconductor memory device for alternately selecting two groups of input/output lines according to a predetermined column address. A first group of a number of the input/output line pairs is driven by activation of any one of the selection signals within the first group, and a second group of a number of the input/output line pairs is driven by activation of any one of the selection signals within the second group. Furthermore, the input/output line pairs within the second group are precharged and equalized when the input/output line pairs within the first group are driven, and the input/output line pairs within the first group are precharged and equalized when the input/output line pairs within the second group are driven.

Abstract: A single-output CCD image sensor selectively transfers a normal or a mirror image without changing the combination of clock signals needed by the HCCD. The CCD image sensor comprises VCCD's arrayed in each row, photodiodes connected to the VCCD's through transfer gates, and an upper HCCD connected to one end of the VCCD's. A rotating part for connecting one end of the upper and lower HCCD's as used for one of the normal or mirror image serial transfers. A control gate formed in parallel between the upper and the lower HCCD is used for the other of the normal or mirror image serial transfers, and operates in parallel. An output circuit is connected to the other end of the lower HCCD.

Abstract: A method for making a semiconductor device having a silicon-on-insulator structure comprises the steps of: forming a pad oxide on a wafer which has a lower silicon substrate, a buried oxide layer and an upper silicon layer, forming an oxynitride region on a predetermined portion of the buried oxide layer; forming an active silicon layer to intersect the oxynitride region, and forming a cavity by wet-etching the exposed oxynitride region; forming a gate insulating layer on the surface of the exposed active silicon layer; forming a polysilicon to fill the cavity surrounding said active silicon layer and removing a predetermined portion of the doped polysilicon to form a gate electrode; and forming source and drain regions on the active silicon layer separated by the gate electrode.

Abstract: A method for manufacturing a LCD device includes forming a first electrode on a lower substrate so as to be connected with an external terminal on the periphery of the lower substrate and forming a liquid crystal cell on a central portion of the lower substrate. A passivation layer is thereafter formed on the overall surface of the lower substrate. A first portion of the passivation layer which overlies a contact area of the first electrode is then removed using a laser beam directed through the lower substrate at the contact area of the first electrode and the overlying passivation layer. A conductive layer of paste is formed on the contact area of the first electrode, either before or after the removal of the first portion of the passivation layer, and an upper substrate is assembled to the lower substrate so that the conductive layer forms an electrical connection between the first electrode and a common electrode formed on an inner surface of the upper substrate.

Abstract: A process for formation of a thin film transistor liquid crystal display is disclosed, in which an etch-back type 3-mask process or an etch stopper type 4-mask process is applied, so that the semiconductor layer of the thin film transistor can be isolated from the data line. Consequently, the optical leakage current which aggravates the performance of the transistor is inhibited. Further, the data line is composed of a material which has a low chemical reactivity with ITO, so that a corrosion due to a chemical reaction between the data line and ITO can be eliminated.

Abstract: A method for forming a fine pattern, e.g., for forming the storage electrodes of the capacitors of the memory cells of semiconductor memory devices, which includes the steps of depositing a mask layer on the layer to be patterned, depositing a photoresist layer on the mask layer, patterning the photoresist layer, to thereby form a photoresist pattern, anisotropically etching the mask layer, using the photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of the photoresist pattern and the mask layer pattern, and, etching the layer to be patterned using the composite layer and the etch by-products as an etching mask, to thereby form a fine pattern. The mask layer is made of a material, e.g., a high-temperature oxide, having different physical properties than that of the photoresist. Further, the anisotropic etching process is preferably carried out by means of a plasma etching process using a mixture of CF.

Abstract: A charge-coupled device type image sensor having a floating diffusion-type amplifier including a drive transistor comprising a substrate, a drain region, a source region, a depletion channel region formed between the drain and source regions in contact with the drain region, and a gate electrode formed on the substrate between the source region and the drain region, such that the gate electrode overlays a portion of the source region and overlays a portion of the depletion channel region, wherein the drain region is spaced apart from said gate electrode.