Abstract: A semiconductor memory device which includes, in a first embodiment, a first PMOS transistor having a source electrode coupled to a signal transport line, a second PMOS transistor having a source electrode coupled to an inverted signal transport line, a drain electrode coupled to a gate electrode of the first PMOS transistor, and a gate electrode coupled to a drain electrode of the first PMOS transistor, a first current limiter connected between the drain electrode of the first PMOS transistor and a reference potential, a second current limiter connected between the drain electrode of the second PMOS transistor and the reference potential, a first constant current source connected between a supply voltage and the source electrode of the first PMOS transistor, and, a second constant current source connected between the supply voltage and the source electrode of the second PMOS transistor.

Abstract: A semiconductor memory device having a plurality of memory blocks and a plurality of I/O control circuits operatively associated with respective ones of the memory blocks. Each of the I/O control circuits includes a flash write enable signal generator responsive to a flash write mode indication signal and a respective memory block address signal, for generating a memory block specific flash write enable signal. Each of the I/O control circuits further includes a plurality of first column selectors connected between respective first alternate pairs of bit lines and respective first data input/output lines, a plurality of second column selectors connected between respective second alternate pairs of bit lines and respective second data input/output lines, and a plurality of flash write control logic circuits responsive to the memory block specific flash write enable signal and a respective one of a plurality of column select signals for generating a corresponding plurality of column selector drive signals.

Abstract: A nonlinear optical device, operating in an optical bistability mode, capable of carrying out amplification, commutation, switching and computing of optical signals, comprises, a pair of directional couplers formed by optically coupling a pair of waveguides and a pair of nonlinear circular resonators and an optical transistor incorporating an optical mixer of bifurcation optical active type capable of functioning also as a phase modulator.

Abstract: A nonvolatile semiconductor memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. A selected memory block is erased by an erase voltage applied to a semiconductor substrate while unselected memory blocks are prevented from erasing by capacitive coupling of the erase voltage to floated word lines connected to control gates of memory transistors of the unselected memory blocks. In a program mode where a program voltage is applied to a selected word line of a selected memory block and a pass voltage is applied to unselected word lines of the selected memory block, channel regions and source and drain junctions of memory transistors of cell units in the selected memory block are charged to a program inhibition voltage.

Abstract: The present invention pertains to semiconductor memory devices and more particularly to a burn-in circuit of such devices and burn-in method which improve reliability of a static random access memory RAM.

Abstract: An input buffer includes a low-speed input buffer for buffering an input signal at the time of low-speed operation, a high-speed input buffer being controlled by the low-speed input buffer, for adjusting the high-level and low-level logic of an input signal at the time of high-speed operation and an output driver for outputting high-level or low-level logic by inputting the output signal of the high-speed input buffer. Therefore, there is no direct current present, the operational speed is increased and noise can be reduced.

Abstract: In a method for forming a compound oxide film such as a gate oxide film of a MOS device, after a first oxide film (such as a HTO film) is formed on a semiconductor substrate by deposition at a high temperature, a second oxide film is formed below the first oxide film by wet oxidizing the surface of the semiconductor substrate, which results in a compound oxide film consisting of the HTO film and the wet oxide film. Therefore, a high quality oxide film having excellent electrical characteristics can be formed.

Abstract: A parallel test circuit is provided in a semiconductor memory chip for use during both a wafer test and a package test. The parallel test circuit operates to automatically reduce the number of test output pins associated with a single package test to thereby increase the number of packages that can be tested simultaneously. The parallel test circuit includes a selector for limiting the number of output pads which may be activated during a package test run. The selector is responsive to a wafer test enable signal, from a selection control circuit, to control output pad selection.

Abstract: A semiconductor memory device has a plurality of memory cell arrays, each with a normal cell array and a spare cell array. Fuse circuits are programmable to substitute a spare-cell-array word line for a defective word line in any normal cell array. When a defective word line is addressed, a fuse circuit activates a spare-cell-array word line, and also activates a redundancy signal line. A single redundancy signal line is shared by all fuse circuits and block select circuits. Block select circuits normally enable the cell array that includes the defective word line, however, the block select circuits are disabled when the defective word line has been replaced by a spare word line an another block.

Abstract: A lead frame for a semiconductor device used in a vertically surface-mounted package which has internal leads gathered on one side thereof includes separately formed dummy leads attached to a semiconductor chip on the opposite side of the lead frame to avoid an inconsistent inflow pressure of a molding material during a package molding process caused by gathering of the internal leads on only one side, thereby enhancing reliability of the semiconductor package. There is also no need to separately form a heat sink structure for eliminating heat of the semiconductor chip since the dummy leads function as the heat sink.

Abstract: A nonvolatile memory device containing sub memory arrays and distinct associated peripheral sub array circuits containing error checking and correction circuits that are similarly positioned according to the sub array. The memory device is configured so that a single mask change allows the device to be manufactured as a normal mode device or a page mode device.

Abstract: A liquid crystal display and manufacturing method therefor. The liquid crystal display includes two opposing electrodes, a plurality of electric-field-effect liquid crystal layers disposed between the two electrodes, insulating layers for dividing the liquid crystal layers, main supports for maintaining a predetermined distance between the insulating layers, and auxiliary supports provided about liquid crystal injection holes through the insulating layers, the auxiliary supports preventing the deformation of the liquid crystal injection holes and facilitating the injection of liquid crystal.

Abstract: In video signal processing circuitry detail enhancement is done on each of three color channels in response to the detail information, the enhancement of the detail in each color channel being done in reliance on separated high-spatial-frequency information originally contained in one or more of the channels. The high-spatial-frequency information is separated by differentially combining a fullband video signal with that signal as filtered by a cascade connection of vertical lowpass filter and horizontal lowpass filter.

Abstract: A word line driver circuit for use in a semiconductor memory device for driving a word line of the memory device to a word line driving voltage having a voltage level greater than that of a power supply voltage includes a control circuit and a word line driving circuit. The word line driving circuit includes a pull-up transistor which is connected in series between the word line driving voltage and the word line, a transfer transistor connected in series between a row decoding signal and the gate electrode of the pull-up transistor. The control circuit generates a transfer output signal which is applied to the gate electrode of the transfer transistor. In a first operating mode, the transfer output signal has a voltage level greater than the power supply voltage by an amount equal to the threshold voltage of the transfer transistor, and, in a second operating mode, the transfer output signal has a voltage level equal to the power supply voltage.

Abstract: A burn-in enable circuit and burn-in test method of a semiconductor memory device are disclosed. A high voltage exceeding the external power voltage by a predetermined amount is applied to at least one of a plurality of pins normally used with a connected semiconductor memory chip to initiate a burn-in test mode. The burn-in test enable circuit senses this high voltage and causes the reset operation of word lines in the chip to become disabled. This allows for a high stress voltage to be applied to all access transistors in the chip simultaneously during a burn-in test for substantially the same amount of time. Therefore, burn-in time is substantially reduced and a reliable burn-in test is obtained.

Abstract: A circuit which is particularly useful as a chip initialization signal generating circuit for initializing the circuits of a semiconductor memory device includes a time delay circuit for generating a second signal a predetermined time after a first signal, e.g., a power supply voltage, is applied thereto, a first inverter for generating a third signal having a first logic level when the second signal is below a trip point level of the first inverter, and a second logic level when the second signal is above the trip point level, and, a trip point level raising circuit coupled to the first inverter for raising the trip point level.

Abstract: A capacitor of a semiconductor device has a plate electrode which process margin and a method of manufacturing same are disclosed. The plate electrode has a planarized surface and borders a source region. A recessed field oxide layer defining an active region is formed on a semiconductor substrate. Then, an insulating pattern for self-aligning an electrode is formed on the active region. The insulating pattern has a step with respect to the field oxide layer. Thereafter, a trench is formed in the semiconductor substrate by partially removing the field oxide layer, the insulating pattern and a surface portion of the semiconductor substrate. A conductive material is deposited on the semiconductor substrate having the trench and the insulating pattern to form a conductive layer filling the trench. Then, the conductive layer is polished until the insulating pattern is exposed, to thereby obtain an electrode having a planarized surface.

Abstract: A level shifter and a data output buffer adapted for use in a semiconductor memory device including a memory cell for storing data, a sense amplifier for amplifying data read from the memory cell and generating an ECL-level output signal, and a level shifter for converting the ECL-level output signals into a CMOS-level signal, wherein the level shifter has a level shifting means receiving the ECL-level data signals, converting the input data to CMOS-levels, and outputting a result, and a delay for delaying the result so as to control its current consumption of the level shifter.

Abstract: An LCD having quick response time and sharp contrast provides for a dense white display when using a reflective-type LCD and the desired color density when using a backlight. This LCD is made up of a plurality of field-effect type liquid crystal layers alternately stacked with light-transmitting electrically insulating material layers. The thickness of each liquid crystal layer is desirably less than 3 .mu.m, and that of each electrically insulating material layer is desirably less than 5 .mu.m. The electrically insulating material employs a semiconductor, a metal oxide, or a light-transmitting electrically insulating resin including epoxy resin and acryl resin. The field-effect type LCD is desirably a nematic, phase-transition or ferroelectric type LCD. The total thickness of the LCD is desirably more than 1 .mu.m.

Abstract: A semiconductor device, e.g., a DRAM, having vertical conduction transistors and cylindrical cell gates, which includes a plurality of spaced-apart trench isolation regions formed in a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a silicon pillar formed on each bit line, a gate insulating layer and gate line formed on each silicon pillar in surrounding relationship thereto, a planarizing layer formed in recesses in the gate lines, an insulating layer formed on the upper surfaces of the gate line and planarizing layer, a plurality of contact holes provided in vertically aligned portions of the insulating layer, the gate line, and the gate insulating layer located above respective ones of the silicon pillars, and, a storage node of a capacitor formed with the contact holes and adjacent surface portions of the insulating layer, in contact with the source region of respective ones of the silicon pillars.