Abstract: Disclosed herein is an all-optical regenerator which is controlled by an external input optical signal for the generation of an output optical signal satisfying certain preset parameters defining the shape and the amplitude of the output optical signal. The optical device comprises a rectangular phase modulator optically coupled between two resonators so that the inlet mirrors of the resonators and the phase modulator form a nonlinear Fabry-Perot interferometer. The phase modulator serves to generate an output signal of a predetermined or desired pulse width and amplitude. The present optical device also includes a multielectrode injection laser which is optically coupled to the phase modulator. The multielectrode injection laser selects the clock frequency and locks output pulses in conformity with the period of the clock frequency.

Abstract: A stacked trench capacitor including a first trench formed in a semiconductor substrate, an insulating material, preferably BPSG, substantially filling the first trench to thereby define an isolation region of the substrate, a second trench formed in the first trench, the second trench being much narrower and shallower than the first trench, a storage electrode formed on the sidewalls and bottom surface of the second trench, a thin dielectric film formed on the storage electrode, and a plate electrode formed on the thin dielectric film. In a preferred embodiment, the isolation region serves to separate and electrically isolate adjacent memory cells of a semiconductor memory device, each of the memory cells including a MOSFET transistor and a stacked trench capacitor constructed as described above.

Abstract: A semiconductor device which includes a semiconductor integrated circuit chip provided with a plurality of chip bonding pads contiguous with the peripheral edge of the chip, and a plurality of leads directly bonded to respective ones of the chip bonding pads. The bonding pads are preferably formed within respective notches disposed in a marginal edge portion of the chip, with each of the notches having an open end formed in the peripheral edge of the chip. By locating the chip bonding pads contiguous with the peripheral edge of the chip, rather than a prescribed distance away from the peripheral edge of the chip, the bonding pads are directly accessible from the edge of the chip, thereby enabling the leads to be directly bonded to the bonding pads, and thus eliminating the need for bonding bumps or balls.

Abstract: The present invention relates to a MESFET in which source and drain regions with inverse slopes are formed on a semi-insulating semiconductor substarate having the insulating layer by using the growth property according to the crystal direction and a channel is electrically separated from the substrate by forming the channel layer and a self-aligned gate electrode sequentially on the top of the void formed by the inverse slopes of the source and drain regions. Thus, the present invention achieves the suppression of the leakage current and the backgating effect without the formation of a buffer layer, the formation of the gate electrode without misalignment, a short effective gate length and a low gate resistivity, thereby operating at high speed.

Abstract: A semiconductor memory device having a NAND-type memory cell structure for preventing the occurrence of an electrical bridge resulting from impurity particles generated during a manufacturing process. The space between the word-line whereto a Vcc voltage is applied and the string selection line whereto a Vss voltage is applied and a space between the string selection line of the string selection transistor and the word-line of the cell transistor adjacent to the string selection transistor, are wider than that between the word-lines so as to prevent early stand-by current failure caused by the special stand-by conditions of a NAND-type memory cell. Therefore, the occurrence of a polysilicon bridge between the word-line and the string selection line due to impurity particles generated during the manufacturing process is prevented. As a result, a defectively manufactured chip can be resurrected by the data correction means provided within the memory device.

Abstract: A method for manufacturing BiCMOS semiconductor devices in which an oxide layer formed on the surface of a semiconductor substrate for the purpose of facilitating formation of spacers adjacent to sidewalls of the gates of the MOS transistors thereof is only partially removed, by using a dry etching process, to thereby leave a residual oxide layer, which is then removed, by using a wet etching process, to thereby form the spacers. Alternatively, all portions of the oxide layer except a portion thereof overlying the base-emitter region of the bipolar transistor of the BiCMOS device is removed, thereby precluding the necessity of etching the oxide layer away at the base-emitter junction. In either case, the DC forward current gain Hfe and linearity of the bipolar transistor of the BiCMOS device are enhanced.

Abstract: Disclosed is a non-volatile semiconductor memory device and the manufacturing method thereof. The non-volatile semiconductor memory device comprising a semiconductor substrate, and a group of gates electrically isolated from each other and formed on the semiconductor substrate, wherein the group of gates comprises a floating gate formed with a first conductive layer, a control gate formed with a second conductive layer laminated on the floating gate and select gates formed with the first conductive layer and the second conductive layer/formed on both the opposite side of the floating gate and the control gate and with an interposing impurity diffusion region formed on the semiconductor substrate, and wherein the select gates formed with the first conductive layer and the second conductive layer forms contacts on a field oxidation layer, thereby being connected with each other.

Abstract: A method for manufacturing a semiconductor device which utilizes anodic oxidation. A first semiconductor layer of a first conductive type is formed on an insulating substrate, a highly doped second semiconductor layer of the first conductive type is formed on the first semiconductor layer, and then an anti-oxidizing pattern is formed on the second semiconductor layer to expose a predetermined portion of the second semiconductor layer. After forming the anti-oxidizing pattern, anodic oxidation is performed to oxidize the exposed portion of the second semiconductor layer. Instead of employing a conventional plasma etching process for removing the portion of the ohmic contact layer which is not in contact with the source and drain electrodes, the portion of the ohmic contact layer to be removed is subjected to anodic oxidation, to thereby form an anodic oxidation layer, thus facilitating removal of the unnecessary portions of the ohmic contact layer without the use of a plasma etching step.

Abstract: A column redundancy circuit for a semiconductor memory device, e.g., a DRAM, which includes a normal memory array comprised of a plurality of memory blocks each comprised of a matrix of rows and columns of memory cells, with at least two of the memory blocks sharing common columns, and with at least one of the columns being defective, in the sense of being connected to at least one memory cell which has been determined to be defective.

Abstract: A circuit for generating an internal source voltage which is applied to the memory elements of a semiconductor device. The circuit includes a reference voltage generating circuit for generating a reference voltage, a comparator for comparing the internal source voltage with the reference voltage, a driver for driving an external source voltage into the internal source voltage under the control of the comparator, and a low reference voltage generating circuit for generating a control signal to fully turn on the driver when the voltage level of the external source voltage is lower than the voltage level of the reference voltage generating circuit and which prevents the driver from receiving the output signal of the comparator so as to apply the external source voltage to the memory element of the memory device.

Abstract: A device isolation method for use in a process for manufacturing a semiconductor device, in which a pad oxide layer and a nitride layer are sequentially formed on the surface of a semiconductor substrate, an opening for defining the device isolating region is formed, and the substrate is oxidized at a high temperature to form a field oxide layer. Before the field oxide layer is formed, the nitride layer and pad oxide layer are etched to form a nitride layer spacer on the sidewalls of the pad oxide layer, to suppress the creation of a bird's beak due to lateral diffusion of oxygen between the pad oxide layer and nitride layer. In one embodiment, the nitride layer spacer is formed while leaving part of the pad oxide layer on the substrate, and the lower periphery of the spacer is undercut to be filled with an oxidizable material, thereby minimizing lateral diffusion of oxygen during the oxidation step.

Abstract: A comparator with hysteresis in which a reference voltage of the comparator is easily adjustable. A resistor for dropping the reference voltage and a current source are coupled to a reference voltage terminal, and function to adjust the reference voltage in response to the level of an output voltage. Thus, the hysteresis voltage of the comparator can be easily adjusted by varying the current flowing through the resistor.

Abstract: A semiconductor memory device which is comprised of a plurality m of electrically isolated data memory sub-arrays for storing data bits and a plurality k of electrically isolated parity memory sub-arrays for storing parity bits, wherein each of the data and parity memory sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the memory cells in each row connected to a common word line and the memory cells in each column connected to a common bit line. Row address decoders function to activate a selected word line in each of the memory sub-arrays, and column address decoders, in combination with column selection circuitry, function to couple a selected bit line in each of the memory sub-arrays to a plurality m of sense amplifiers, which function to sense the voltage level of respective ones of the selected bit lines, and produce output data and parity bits representative of these sensed voltage levels.

Abstract: A data output buffer suitable for use in a semiconductor memory device includes a first input circuit coupled to a first data signal and a first control signal, e.g., an output enable signal, and a second input circuit coupled to a second data signal which is the inverse of the first data signal and the first control signal. The data output buffer also includes a pull-up circuit responsive to the output of the first input circuit for selectively raising the data output node to a high voltage level, e.g., Vcc, and a pull-down circuit responsive to the output of the second input circuit for selectively lowering the data output node to a low voltage level, e.g., Vss. The data output buffer further includes a preset circuit comprised of a first preset control circuit responsive to the output of the first input circuit and a second control signal, e.g., an inverse output enable signal, for selectively raising the data output node from the low voltage level to an intermediate voltage level, e.g.

Abstract: A circuit for preventing the false detection of vertical sync pulses included in a video signal which also includes copy guard signals inserted in predetermined intervals thereof, including signal generating circuitry which is responsive to vertical sync pulses separated from the video signal for generating a corrected vertical sync signal, and inhibit circuitry for rendering the signal generating circuitry non-responsive to the separated vertical sync pulses during the predetermined intervals of the video signal, thereby preventing any falsely detected vertical sync pulses due to misinterpretation of the copy guard signals from being included in the corrected vertical sync signal. The inhibit circuitry preferably functions to count a predetermined number of horizontal sync pulses also included in the video signal before allowing any change in the output of the signal generating circuitry.

Abstract: A semiconductor wafer partitioned into a multiplicity of chip areas defined by a grid-like array of scribe lines inscribed into the surface of the wafer, wherein each scribe line is longitudinally bounded by respective field oxide layers formed in the surface of the wafer, to thereby define a scribe line region between adjacent chip areas. The wafer includes a multiplicity of integrated circuits formed in a corresponding multiplicity of the chip areas, respectively, each of the integrated circuits including a patterned, multilayer structure having a peripheral edge portion which extends into a respective one of the scribe line regions, wherein the peripheral edge portion of each multilayer structure has a multi-tiered cross-sectional profile, thereby ensuring adequate step coverage of the photoresist film which is applied to the individual layers of the multilayer structures when they are patterned during the wafer fabrication process.

Abstract: A method for forming a fine pattern of a semiconductor device, in which a first-to-be-patterned layer is formed on a semiconductor substrate, a photoresist film is coated on the first-to-be-patterned layer, and the photoresist film is patterned and cured to obtain a thermally stable photoresist film pattern. Thereafter, a second material layer is formed on the entire surface of the semiconductor substrate on which the photoresist film pattern is formed, by a low temperature plasma method, and the second material layer is anisotropically etched to thereby form a spacer made of the second material layer on the sidewalls of the photoresist film pattern. A first pattern is formed by anisotropically etching the first-to-be-patterned layer, using the spacer and the photoresist film pattern as an etching mask. The spacer and the photoresist film pattern are then removed. Using the first pattern thus obtained, a fine pattern which is the inverse of the first pattern can be formed.

Abstract: A nonvolatile semiconductor memory device having a page program mode of operation. The device including a data input buffer for receiving program data from a data line and a plurality of program voltage generating circuits each of which is selectively operable for generating a program voltage output having a first and second logic level. The device further including a plurality of first selecting MOS transistors coupled to respective ones of the program voltage generating circuits and alternating ones of bit lines included in the memory device and a plurality of second selecting MOS transistors coupled to respective ones of the program voltage generating circuits and a second sequences of alternating one of the bit lines.

Abstract: A refresh timer suitable for use in a semiconductor memory device which has a refresh mode of operation which is enabled by a refresh enable clock signal, and which utilizes an operating voltage having a plurality of different operating levels, Vi, where i=1-n, and n is an integer equal to or greater than two. The refresh timer includes a first circuit responsive to the operating voltage for generating a plurality of output voltage signals corresponding to the plurality of different operating voltage levels, respectively. The first circuit includes a plurality of individual voltage detection circuits corresponding to the plurality of different operating voltage levels, respectively, with each ith one of the voltage detection circuits being adapted to detect whether the operating voltage is at the corresponding ith level, and to drive the corresponding ith one of the output voltage signals high when it is detected that the operating voltage is at the corresponding ith level.

Abstract: A method for manufacturing BiCMOS semiconductor devices in which an oxide layer formed on the surf ace of a semiconductor substrate for the purpose of facilitating formation of spacers adjacent to sidewalls of the gates of the MOS transistors thereof is only partially removed, by using a dry etching process, to thereby leave a residual oxide layer, which is then removed, by using a wet etching process, to thereby form the spacers. Alternatively, all portions of the oxide layer except a portion thereof overlying the base-emitter region of the bipolar transistor of the BiCMOS device is removed, thereby precluding the necessity of etching the oxide layer away at the base-emitter junction. In either case, the DC forward current gain Hfe and linearity of the bipolar transistor of the BiCMOS device are enhanced.