Abstract: A semiconductor memory device includes two latch circuits, each for holding data corresponding to a single normal address. When sequentially used, one after the other, one latch circuit can be storing new data while the other latch circuit outputs its data to the page decoder for subsequent output. Thus, data access delay times for page mode operation are further reduced because the delay which typically results from addressing a normal address is eliminated.

Abstract: A constant voltage generator having a substrate voltage pumping circuit, a voltage pumping circuit and a single oscillator for generating pulses to which the substrate voltage pumping circuit and the voltage pumping circuit are commonly responsive, reducing current consumption of a semiconductor memory device during a stand-by state thereof.

Abstract: A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.

Abstract: In a semiconductor memory device, and in particular in a NAND-type ROM memory cell, the transistors of a memory cell region and a peripheral circuit portion are manufactured to include a first and second impurity regions. The second impurity region has a higher impurity density impurity than the first impurity region. A third impurity region is added which has a higher impurity density and shallower depth than the impurity density of the first impurity region. Accordingly, the conventional transistor structure of the peripheral circuit portion is maintained while the transistors of the memory cell are optimized to have ideal electrical characteristics, including an increased current driving capability.

Abstract: A semiconductor memory device including a memory cell array which is formed of each of memory cells connected to intersection of a plurality of bit lines and word lines is provided such that, during designing the layout, a length of a storage electrode of the outermost memory cell in the memory cell array is longer than that of a storage electrode of an inner memory cell, or a spacing between two bit lines in the periphery of the memory cell array is longer than that between bit lines in the inner portion of the memory cell array, or a width of an active region of the outermost memory cell is wider than that of an active region of the inner memory cell, thereby forming a metal layer having an excellent step coverage by means of only the layout arrangement without additional processes while being not concerned about the structure of a storage electrode.

Abstract: A liquid crystal display device having a multilayer structure includes at least one substrate, first electrodes arranged on the substrate into a predetermined pattern for constituting a plurality of pixels and second electrodes arranged across from the first electrode by a predetermined interval therebetween, liquid crystal layers filling the gap between the electrodes, at least one insulation layer arranged between the liquid crystal layers for separating the liquid crystal layers into a multiple lamination structure, columns having protrusions extending radially and outwardly between the upper and lower insulation layers at each vertical level of outer walls for securing the insulation layer within the liquid crystal layer, and protective insulation layers for protecting the first and second electrodes.

Abstract: Disclosed is a dynamic random access memory device (DRAM) having an increased cell capacitance and simplified manufacturing method thereof. The storage electrode the capacitor of the DRAM is connected to a semiconductor substrate through an opening formed in an insulating layer, and has a structure having an outer peripheral wall portion with a laterally extending bottom on the insulating layer and an inner central pillar portion including a hole of a certain depth within the opening in the center of the outer peripheral wall portion. Thus, cell capacitance is greatly increased within a limited unit cell area, its reliability is enhanced, and the manufacturing process is distinctly simplified.

Abstract: An illumination system for a projection exposing apparatus having an improved fly's eyes lens is disclosed in which an individual lens of a fly's eyes lens includes a pattern portion having a plurality of annuluses with the same center but different diameters, and an etch portion disposed alternately with the pattern portion. The etch portion is formed to have a phase difference of 180 degrees with respect to the pattern portion.

Abstract: A compressor which is capable of compressing an input signal having an extremely large magnitude, without the signal being distorted and without the necessity of a additional circuit element such as an automatic level controller external thereto. The compressor includes a summing amplifier, a full-wave rectifier, an active limiter, and a gain controller. The summing amplifier compresses an input signal and produces a compressed output signal which is a compressed version of the input signal. The full-wave rectifier full-wave rectifies the compressed output signal and converts the rectified compressed output signal to a DC voltage output, and converts the DC voltage output to a first DC output. The active limiter compares the DC voltage output with a prescribed limit voltage, and is only enabled when the DC voltage output is greater than the limit voltage to produce a second DC output which is proportional to the difference between the DC voltage output and the limit voltage.

Abstract: A projection exposure system includes a light source, a parallel-light forming lens and a fly's eyes lens which are sequentially disposed along a light traveling path. Between the parallel-light forming lens and fly's eyes lens is provided a light dispersing device which is composed of a first light dispersing lens with a concave lens or a second light dispersing lens with multiple small convex lenses. The light dispersing device diverges central light incident on the fly's eyes lens, to thereby increase peripheral light intensity. Accordingly, in tilted illumination, which uses peripheral light, light utilizing efficiency is raised.

Abstract: A method of manufacturing a multi-layered liquid crystal for a liquid crystal display device in which an electric-field effect type liquid crystal layer is placed between opposing upper and lower electrodes and a plurality of insulating layers are alternately stacked with the liquid crystal layer, includes the steps of forming a lower electrode on a substrate, alternately stacking an insulating layer and a source material layer having a selective dissolving characteristic for forming cavities for a liquid crystal layer, and performing a selective dissolution and liquid crystal injection through well-shaped holes. The method does not need an additional step of forming columns for supporting the liquid crystal layer, thereby achieving a cost reduction. The manufactured product has a much higher light dispersion effect.

Abstract: A data output circuit of a semiconductor memory device matches an equalizing level of voltages at data lines in a pair with a logic threshold voltage of data output buffers. The data output circuit having an equalizing transistor connected between first and second nodes connected to the outputs of a sense amplifier, includes a threshold voltage control circuit disposed between the sense amplifier and the data output buffers for allowing a threshold voltage of the data output buffers to match with the equalizing level of the voltages at the first and second nodes. The threshold voltage control circuit has the same structure and characteristics as that of the output buffers, so as to ensure that the logic threshold voltage of the data output buffers matches with the equalizing level of the voltages at the first and second nodes.

Abstract: A drum servo system controls rotation of a head drum stably, even though a DFG signal has been dropped out. The drum servo system includes a DFG signal dropout detector for detecting the dropout of the DFG signal to generate first and second switching signals according to the detection. A digital-to-analog converter generates a drum motor driving voltage in dependence upon the first switching signal when the DFG signal is in a normal state and upon the second switching signal when the DFG signal is in an abnormal state. When the DFG signal is in the abnormal state, a previous state of the DFG signal is used for generating the drum motor driving voltage so that the head drum may rotate stably regardless of the dropout of the DFG signal.

Abstract: A method for making a polycrystalline silicon (p-Si) thin film by heat treating an amorphous silicon (a-Si) thin film using a laser beam, including the steps of forming an a-Si thin film over a substrate, forming a metal reflection film over the a-Si thin film, forming, in the metal reflection film, windows each having a width smaller than the width of the regular strong energy portion of laser beam, annealing the portions of a-Si thin film disposed beneath the windows using a laser beam, removing the remaining portions of metal reflection film, each having a width smaller than the width of the regular strong energy portion of laser beam, to expose the portions of a-Si thin film disposed beneath the remaining portions of metal reflection film, and annealing the thus exposed portions of a-Si thin film disposed beneath the remaining portions of metal reflection film.

Abstract: A video signal processing circuit of a CCD-type color video camera includes a gamma-correcting circuit section, a delay circuit section, a chrominance signal processor and a luminance signal processor. Accordingly, the circuit is configured such that gamma-compensation processing is performed before the separation of the luminance and chrominance signals, and a DC fluctuation due to the gamma-compensation processing is compensated in the luminance signal processor. Thus, horizontal noise caused by the gamma correction can be eliminated, which not only improves picture quality but also enables a reduction in chip size.

Abstract: A row redundancy circuit for use in a semiconductor memory device. The row redundancy circuit providing fuse boxes to repair defective normal memory cells even in the adjacent normal memory cell arrays.

Abstract: A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via) and a first conductive layer formed on the insulating layer which completely fills the opening. The first conductive layer does not produce any Si precipitates in a subsequent heat-treating step for filling the opening with the first conductive layer material. The semiconductor device may further include a second conductive layer having a planarized surface on the first conductive layer. This improves subsequent photolithography. An anti-reflective layer may be formed on the second conductive layer for preventing an unwanted reflection during a photo lithography process.

Abstract: A method for forming an inter-metal dielectrics in a semiconductor device includes the steps of sequentially forming a first and second insulating layers over a semiconductor substrate with a patterned metal layers, etching-back the second insulating layer so as to form second insulating spacers over the side walls of the first insulating layer, and growing a third insulating layer over the first and second insulating layers, the growing speed of the third insulating layer being different from the region over the first insulating layer to the region over the second insulating layer.

Abstract: A method for determining the original location of each of a multiplicity of semiconductor chips fabricated on a common wafer, including the step of applying location identification data to each of the chips, wherein the location identification data is indicative of the original location of the chip on the wafer. The applying step is preferably performed during the process for fabricating the chips on the wafer, for example, by means of using a photomask in a conventional photolithographic process to etch a location identification mark on a predetermined layer of each chip. The location identification mark can be, for example, a dot matrix pattern which signifies the original location of the chip to which it is affixed on the wafer on which it was fabricated, in accordance with a binary coding scheme.

Abstract: The present invention provides a semiconductor device having a capacitor that is formed through: a first step of forming a polysilicon layer having a rough surface after a nonconductive layer is applied to a base substrate; a second step of etching back away the polysilicon layer to expose the nonconductive layer and thus remaining islandlike polysilicon layers; a third step of etching the nonconductive layer, using the remained polysilicon layers as an etching mask; a fourth step of etching the base substrate of the capacitor, using the nonconductive layer as a mask; a fifth step of forming a pattern of the base substrate of the capacitor after the removal of the remained nonconductive layer; a sixth step of forming an upper substrate of the capacitor after the formation of a dielectric film of the capacitor. According to this invention, the surface area of the capacitor electrode is remarkably enhanced such that the integrity of DRAMs is more improved.