Patents Represented by Attorney Christopher P. Maiorana, PC
  • Patent number: 8347304
    Abstract: A method of resource allocation failure recovery is disclosed. The method generally includes steps (A) to (E). Step (A) may generate a plurality of resource requests from a plurality of driver modules to a manager module executed by a processor. Step (B) may generate a plurality of first calls from the manager module to a plurality of allocation modules in response to the resource requests. Step (C) may allocate a plurality of resources to the driver modules using the allocation modules in response to the first calls. Step (D) may allocate a portion of a memory pool to a particular recovery packet using the manager module in response to the allocation modules signaling a failed allocation of a particular one of the resources. Step (E) may recover from the failed allocation using the particular recovery packet.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: January 1, 2013
    Assignee: LSI Corporation
    Inventors: Jose K. Manoj, Chennakesava R. Arnoori, Atul Mukker
  • Patent number: 8339887
    Abstract: An apparatus comprising a write data buffer circuit, a memory, and a read data buffer circuit. The write data circuit may be configured to present data in a second format in response to data received in a first format. The memory may be configured to (i) receive the data in the second format and (ii) present the data in the second format. The read data buffer circuit may be configured to (i) receive data in the second format and (ii) present data in a third format. The memory may be configured to allow two reads or two writes during a single clock cycle of reference clock without encountering a data overflow condition.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 25, 2012
    Assignee: LSI Corporation
    Inventors: Nahum N. Vishne, Lior L. Bandel, Nimrod Alexandron
  • Patent number: 8340196
    Abstract: A method of generating a motion menu in a low memory environment. The method generally includes the steps of (A) generating a plurality of encoded streams in a buffer by encoding a fixed duration from each of a plurality of title streams received in a video program, (B) generating a plurality of thumbnails frames in the buffer by decoding each of the encoded streams and (C) generating the motion menu in the buffer by combining one of the thumbnail frames from each respective one of the encoded streams into a respective one of plurality of menu frames such that a sequential display the menu frames appears as a plurality of thumbnails having dynamic content in the motion menu.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: December 25, 2012
    Assignee: LSI Corporation
    Inventor: Laszlo Weber
  • Patent number: 8339891
    Abstract: An apparatus comprising a plurality of buffers and a memory controller. The plurality of buffers may each be configured to generate an access request signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The memory controller circuit may be configured to generate a clock enable signal in response to the plurality of access request signals. The clock enable signal may be configured to initiate entering and exiting a power savings mode of a memory circuit.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: December 25, 2012
    Assignee: LSI Corporation
    Inventors: Eskild T. Arntzen, Jackson L. Ellis
  • Patent number: 8334715
    Abstract: An apparatus comprising a first circuit, a state machine, a compare circuit and a calibration circuit. The first circuit may be configured to generate a slew rate control signal and a calibration signal in response to (i) a plurality of control bits and (ii) an operation signal. The state machine may be configured to generate the operation signal and a plurality of intermediate control signals in response to (i) a compare signal and (ii) clock signal. The compare circuit may be configured to generate the compare signal in response to (i) a reference voltage and (ii) a capacitance signal. The calibration circuit may be configured to generate the capacitance signal in response to (i) the calibration signal and (ii) the plurality of intermediate control signals.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: December 18, 2012
    Assignee: Ambarella, Inc.
    Inventors: Harish S. Muthali, Xiaojun Zhu
  • Patent number: 8336018
    Abstract: A global power distribution network in an integrated circuit comprising a first layer of conductive material and a second layer of conductive material. The first layer of conductive material may be (i) coupled to one or more power supplies and (ii) configured to form a plurality of first rails of a mesh. The first rails may (a) supply power to one or more components of a core logic of the integrated circuit, (b) be aligned with a first axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh has a uniform voltage gradient from a perimeter of the integrated circuit to a center of the integrated circuit along the first axis. The second layer of conductive material may be (i) coupled to the one or more power supplies and (ii) configured to form a plurality of second rails of the mesh.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: December 18, 2012
    Assignee: LSI Corporation
    Inventors: Mark F. Turner, Jonathan W. Byrn, Jeffrey S. Brown
  • Patent number: 8332546
    Abstract: An apparatus generally having a processor and a direct memory access controller is disclosed. The processor may be configured to increment a task counter to indicate that a new one of a plurality of tasks is scheduled. The direct memory access controller may be configured to (i) execute the new task to transfer data between a plurality of memory locations in response to the task counter being incremented and (ii) decrement the task counter in response to the executing of the new task.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: December 11, 2012
    Assignee: LSI Corporation
    Inventors: Leonid Dubrovin, Alexander Rabinovitch
  • Patent number: 8325793
    Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate an equalized signal in response to an input signal and an equalizer parameter signal. The equalizer parameter signal generally causes a cancellation of pre-cursor inter-symbol interference from a plurality of symbols in the input signal. The second circuit may be configured to generate (i) the equalizer parameter signal, (ii) a control signal and (iii) a data output signal in response to the equalized signal. The control signal generally causes an adjustment of the equalizer parameter signal. The adjustment of the equalizer parameter signal generally causes a decrease in the pre-cursor inter-symbol interference from the symbols.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: December 4, 2012
    Assignee: LSI Corporation
    Inventor: Lizhi Zhong
  • Patent number: 8324927
    Abstract: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 4, 2012
    Assignee: LSI Corporation
    Inventors: Dharmesh Bhakta, Hong-Him Lim, Cheng-Gang Kong, Todd Randazzo
  • Patent number: 8324019
    Abstract: A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: December 4, 2012
    Assignee: LSI Corporation
    Inventors: George C. Tang, Lizhi Zhong, Freeman Y. Zhong, Wenyi Jin, Jeffrey A. Hall
  • Patent number: 8312499
    Abstract: A method for conveying private or enhancement information in a compressed bit stream comprising the steps of (A) generating a compressed bit stream in response to a first data stream and a plurality of encoding choices and (B) controlling the encoding choices in response to a second data stream comprising one or both of the private information and the enhancement information.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: November 13, 2012
    Assignee: LSI Corporation
    Inventors: Elliot N. Linzer, Aaron G. Wells
  • Patent number: 8311101
    Abstract: An apparatus comprising an estimation circuit, a rate control circuit, a queue circuit, and an encoder circuit. The estimation circuit may be configured to generate a size value in response to an input signal comprising (i) a plurality of frames and (ii) a plurality of embedded subtitle elements. The rate control circuit may be configured to (i) generate a control signal, (ii) pass through the plurality of frames, (iii) present a first one or more of subtitle elements for current processing in response to the size value, and (iv) present a second one or more of subtitle elements for subsequent processing. The queue circuit may be configured to (i) receive the second one or more subtitle elements, (ii) present the second one or more of subtitle elements for current processing when the control signal is in a first state and (iii) hold a second one or more subtitle elements for subsequent processing when the control signal is in a second state.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: November 13, 2012
    Assignee: LSI Corporation
    Inventors: Gregory R. Maertens, Diego Vianello
  • Patent number: 8312072
    Abstract: An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: November 13, 2012
    Assignee: LSI Corporation
    Inventors: Sergei B. Gashkov, Alexandre Andreev
  • Patent number: 8310776
    Abstract: An apparatus comprising a control circuit, a driver circuit and a write head. The control circuit may be configured to generate a plurality of control signals in response to a data input signal. The driver circuit may be configured to generate a differential write control signal in response to the plurality of control signals. The driver circuit may receive the plurality of control signals through a flexible bus. The driver circuit may be located remotely from the control circuit. The write head may be configured to write information by physically moving above one of a plurality of tracks on a disk in response to the write control signal. The driver circuit may be configured to move along with the write head.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: November 13, 2012
    Assignee: LSI Corporation
    Inventor: Ross S. Wilson
  • Patent number: 8296782
    Abstract: A method for capturing data comprising the steps of (A) handling a call for a first operating system at a storage library, (B) routing the call from the storage library to a controller firmware, (C) sending a response to the call from the controller firmware to the storage library, and (D) storing the response in a data store box for later use by the storage library.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: October 23, 2012
    Assignee: LSI Corporation
    Inventors: Mahmoud K. Jibbe, Preeti Badampudi, Soham Kar, Shivprasad Prajapati
  • Patent number: 8295360
    Abstract: A method for implementing a deblocking filter comprising the steps of (A) providing an input buffer storing an unfiltered video frame, (B) providing an output buffer configured to store a filtered video frame, (C) reading pixel values for a plurality of macroblocks from the input buffer into a working buffer, (D) sequentially processing the pixel values in the working buffer through a plurality of filter stages using an array of parallel processors, where each of the plurality of filter stages operates on a different set of pixel values in the working buffer and (E) writing pixel values from a final output region of the working buffer to a respective filter output region of the output buffer.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: October 23, 2012
    Assignee: Elemental Technologies, Inc.
    Inventor: Brian G. Lewis
  • Patent number: 8288260
    Abstract: A process for fabricating a semiconductor device. The process includes (a) growing an n-channel layer of gallium arsenide (GaAs) on a buffer layer, (b) growing a barrier layer on the re-channel layer, (c) epitaxially growing a first etch-stop layer on the barrier layer, (d) growing a first contact layer of wide band-gap material on the first etch-stop layer, (e) epitaxially growing a second etch-stop layer on the first contact layer, (f) growing a second contact layer on the second etch-stop layer, where the second contact layer is a highly doped material, and (g) selectively etching portions of the first contact layer, the second etch-stop layer, and the second contact layer to form a gate region.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 16, 2012
    Assignee: M/A-COM Technology Solutions Holdings, Inc.
    Inventor: Allen W. Hanson
  • Patent number: 8288253
    Abstract: A process for fabricating a semiconductor device. The process including (a) growing a channel layer on a buffer layer, (b) growing a barrier layer on the channel layer, (c) epitaxially growing a quaternary etch-stop layer on the barrier layer, (d) growing a first contact layer on the quaternary etch-stop layer, (e) growing a second contact layer on the first contact layer, (f) etching portions of the second contact layer to reveal a first recess surface, and (g) etching portions of the first contact layer to reveal a second recess surface. The second contact layer may be a highly doped contact layer. The second recess surface generally forms a gate region. The first and the second contact layers have a first etch rate and the quaternary etch-stop layer has a second etch rate in a chosen first etch chemistry.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 16, 2012
    Assignee: M/A-COM Technology Solutions Holdings, Inc.
    Inventors: Allen W. Hanson, Anthony Kaleta
  • Patent number: 8290788
    Abstract: A method and system for interaction with a community of individuals, relating to compliance with and effectiveness of treatment regimens, including supply and use of pharmaceuticals, using a protocol or other intelligent message which acts in place of a service provider and which is capable of collecting or imparting information to patients in place thereof. Individuals interact with the protocol or intelligent message to provide assistance in all aspects of treatment regimen compliance, data collection, supply or delivery, review and modification.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: October 16, 2012
    Assignee: Robert Bosch Healthcare, Inc.
    Inventor: Stephen J. Brown
  • Patent number: 8285934
    Abstract: A method of configuring a storage device is disclosed. The method generally includes the steps of (A) receiving a single data unit over a communication network, the data unit (i) being transferred via the communication network using a standard communication protocol, (ii) defining both (a) a plurality of new configuration items that define a new configuration of the storage device and (b) a command to be performed by the storage device and (iii) having a standard markup language format, (B) calculating at least one configuration change from a plurality of current configuration items to the new configuration items, the current configuration items defining a current configuration of the storage device, (C) adjusting the storage device into the new configuration based on the at least one configuration change and (D) performing a requested operation with the storage device in the new configuration in response to the command.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: October 9, 2012
    Assignee: LSI Corporation
    Inventors: Partha P. Porel, Tanmoy Sil