Abstract: A method for high performance caching is disclosed. The method generally includes steps (A) and (B). Step (A) may fetch a plurality of reference samples of a reference image from a first circuit to a cache of a second circuit. The cache may include a plurality of cache blocks and a plurality of valid bits. Each of the cache blocks generally corresponds to at most one of the valid bits. A size of the cache blocks may match a smallest read access size of the first circuit. Step (B) may transfer the reference samples having the corresponding valid bit set to valid from the cache to a processor of the second circuit.

Abstract: A method for deinterlacing a picture is disclosed. The method generally includes the steps of (A) generating a plurality of primary scores by searching along a plurality of primary angles for an edge in the picture proximate a location interlaced with a field of the picture, (B) generating a plurality of neighbor scores by searching for the edge along a plurality of neighbor angles proximate a particular angle of the primary angles corresponding to a particular score of the primary scores having a best value and (C) identifying a best score from a group of scores consisting of the particular score and the neighbor scores to generate an interpolated sample at the location.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.

Abstract: An apparatus having a cache and a circuit. The cache may store old lines having old instructions. The circuit may (i) receive a first read command, (ii) fetch-ahead a new line having new instructions into a buffer sized to hold a single line, (iii) receive a second read command, (iv) present through a port a particular new instruction in response to both (a) a cache miss of the second read command and (b) a buffer hit of the second read command and (v) overwrite a particular old line with the new line in response to both (a) the cache miss of the second read command and (b) the buffer hit of the second read command such that (1) the first new line resides in all of the cache, the buffer and the memory and (2) the particular old line resides only in the memory.

Abstract: An apparatus including a processor and a memory. The processor may be configured to process pixel data comprising eight or more bits. For pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of the pixel are packed with LSBs from one or more other pixels into a second byte. The memory may be coupled to the processor and configured to store the first byte in response to a first pointer and the second byte in response to a second pointer. The first byte and the second byte are stored independently in the memory.

Abstract: A video transcoder is disclosed. The video transcoder generally comprises a processor and a video digital signal processor. The processor may be formed on a first die. The video digital signal processor may be formed on a second die and coupled to the processor. The video digital signal processor may have (i) a first module configured to perform a first operation in decoding an input video stream in a first format and (ii) a second module configured to perform a second operation in coding an output video stream in a second format, wherein the first operation and the second operation are performed in parallel.

Abstract: An apparatus for a guitar comprising a tremolo anchor, an upper post portion, a lower post portion, and a compressible material. The compressible material is compressible enough to allow for the tightening of the upper post portion but not compressible enough to loosen a guitar string.

Abstract: A method for transitioning a video system is disclosed. The method generally includes a first step for (A) executing in a processing circuit a standby code stored in a nonvolatile memory while the video system is in an off state, the off state defining a low power configuration for the processing circuit and a power off condition for the video system, the standby code being responsive to a plurality of wake up conditions to wake up the video system. In a second step, the method may (B) store an application code in a volatile memory while in the off state, the application code configured to operate the video system while in an on state of the video system. The method generally includes a third step for (C) transitioning from the off state to the on state upon detection of at least one of the wake up conditions. A step for (D) executing in the processing circuit the application code while in the on state to decode video may also exist in the method.

Abstract: A method of compressed picture reconstruction using a plurality of post-processed reference pictures. The method generally includes the steps of (A) generating a first of a plurality of reconstructed pictures by decoding a first of a plurality of compressed pictures using at least one of a plurality of non-post-processed reference pictures buffered in a reference memory, wherein the compressed pictures are received in an input bitstream, (B) generating a first of a plurality of processed pictures by artifact processing the first reconstructed picture to remove artifacts, (C) buffering in the reference memory both (i) the first reconstructed picture as one of the non-post-processed reference pictures and (ii) the first processed picture as one of the post-processed reference pictures and (D) generating a second of the reconstructed pictures by decoding a second of the compressed pictures using at least one of the post-processed reference pictures buffered in the reference memory.

Abstract: An apparatus having a memory and a controller is disclosed. The memory may be configured to (i) store a plurality of cache lines, each of the cache line comprising a plurality of locations including a respective end location and (ii) accessing a particular one of the cache lines identified by a cache address signal. The controller may be configured to (i) buffer a plurality of line pointers, each of the line pointers identifying a respective boundary one of the locations in one of the cache lines and (ii) generate the cache address signal in response to a processor address signal hitting a given one of the locations residing between the respective boundary location and the respective end location.

Abstract: An apparatus comprising a write circuit, a processing circuit and a monitor circuit. The write circuit may be configured to generate one or more write control signals in response to an input signal. The processing circuit may be configured to generate an intermediate control signal in response to (i) the input signal, (ii) a reference clock signal and (iii) one or more user input signals. The monitor circuit may be configured to generate a sample signal in response to (i) the write control signals and (ii) the intermediate signal. The sample signal may represent a waveshape of the write control signals used to monitor writing to a data storage system.

Abstract: A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate an output signal and one or more motion vectors in response to (i) a bitstream signal and (ii) a predictor signal. The second circuit may be configured to generate one or more reference data pixels in response to an address signal and the output signal. The third circuit may be configured to generate the predictor signal and address signal in response to (i) the motion vectors and (ii) the reference data pixels.

Abstract: A method to write data with error checking and correction overlap ranges is disclosed. The method generally includes the steps of (A) receiving plurality of input numbers in a plurality of input signals, (B) generating a plurality of error correction codes by separately operating on each of a plurality of unique pairs of the input numbers, wherein each of the error correction codes is configured to correct at least one error in a corresponding one of the unique pairs and (C) storing the input numbers and the error correction codes in a memory.

Abstract: A method of capturing a still frame is disclosed. The method generally includes the steps of (A) generating a plurality of initial frames with a sensor in response to an optical signal and (B) generating the still frame by combining the initial frames using a noise reduction technique.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a multiplexed signal at a fixed frame-rate in response to a video input signal. The multiplexed signal comprises one of (i) a pre-defined packet which corresponds to a new frame rate detected on the video input signal when in a first mode (ii) repeated video frames at the fixed frame-rate when in a second mode and (iii) augmented digitally repeated frames at the fixed-rate when in a third mode. The second circuit may be configured to generate a video output signal in response to decoding (i) the multiplexed signal at the new frame rate defined by the pre-defined packet when in the first mode or (ii) the repeated video frames on the multiplexed signal at the fixed frame-rate when in the second mode.

Abstract: A method of configurable decoding is disclosed. The method generally includes the steps of (A) receiving a variable value in a configuration signal, (B) calculating a plurality of first syndromes corresponding to a particular codeword of a plurality of codewords received in an input signal, the particular codeword having a plurality of information symbols and a plurality of parity symbols coded such that up to a fixed value of a plurality of errors in the particular codeword are correctable, the fixed value being greater than the variable value, (C) transforming the first syndromes into a plurality of second syndromes such that no greater than the variable value of the errors in the particular codeword are correctable and (D) generating an intermediate signal carrying the second syndromes.

Abstract: A system, apparatus and method for generating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. Various types of data and fields may be provided into the user interface or data template. The location of relevant files, such as a cell or core netlist, may be provided within the template. Additionally, one or more modes may be selected by the user to define the manner in which the ETM file(s) are to be generated. An ETM file is automatically generated using the information provided in the data template.

Abstract: An apparatus comprising a logically contiguous group of at least two drives, a loop and a compression/decompression circuit. Each of the drives comprises (i) a first region configured to store compressed data of a previous drive and (ii) a second region configured to store uncompressed data of the drive. The loop may be connected to the next drive in the logically contiguous group. The compression/decompression circuit may be configured to compress and decompress the data stored on each of the drives.

Abstract: A method for fabricating a transistor and the resulting transistor is disclosed. The method generally includes steps (A) to (E). Step (A) may form a high mobility layer. The high mobility layer is generally configured to carry a two-dimensional electron gas. Step (B) may form a planar layer on the high mobility layer. Step (C) may form a barrier layer on the planar layer. Step (D) may form a doped layer on the barrier layer. The doped layer is generally a low bandgap III-V semiconductor. Step (E) may form a gate in contact with the doped layer. The gate may be separated from both a source and a drain by corresponding ungated recess regions. The high mobility layer, the planar layer, the barrier layer, the doped layer, the source, the gate and the drain are generally configured as a pseudomorphic high electron mobility transistor.