Abstract: A gain enhanced cascoded CMOS amplifier includes: a cascading transistor having its source connected to a folding point node, its drain connected to a first amplifier output terminal, and a gate, the folding point node being coupled to a first power supply terminal; a gain enhancing circuit having a negative input terminal coupled to the first folding point node, a positive input terminal responsive to a first reference voltage source, and an output terminal coupled to the gate of the first cascoding transistor; a first output coupling circuit coupling the first amplifier output terminal to a second power supply terminal; a first input transistor having a gate responsive to a first input voltage, a source, and a drain, the first input transistor having particular physical dimensions; and a first pole-isolating transistor having a drain connected to the first folding point node, a source connected to the drain of the first input transistor, and a gate responsive to an isolation bias voltage, the first pole iso

Abstract: A vented bag includes at least one rectangular sheet of substantially gas-impervious material having a top edge, a bottom edge opposite said top edge, and a first side edge folded over an opposite second side edge to form a tube. The tube has a longitudinal seam including at least first and second overlapping sheet portions joined together along a plurality of seal lines extending longitudinally from said top edge of said sheet to said bottom edge of said sheet. The bag is sealed to closure at one end of said tube. Each of the plurality of seal lines includes a discontinuity proximate one of the top and bottom edges of the sheet. The discontinuities in adjacent ones of the seal lines are disposed proximate opposites ones of the top and bottom edges of the sheet such that the plurality of seal lines, the discontinuities, and the first and second overlapping sheet portions form a tortuous channel providing communication between the interior of the bag and the exterior of the bag.

Abstract: A process is provided for generating a flow chart representing a control program defined by associative relationships between program levels, states and conditions, each condition specifying a transition from an associated one of the states as a source state to a corresponding selected destination state upon satisfaction of the condition during execution of the control program by the logic control unit. Each program level defines a sub-process of the control program.

Abstract: Authentication of a casino game data set is carried out within the casino game console using an authentication program stored in an unalterable ROM physically located within the casino game console. The casino game data set and a unique signature are stored in a mass storage device, which may comprise a read only unit or a read/write unit and which may be physically located either within the casino game console or remotely located and linked to the casino game console over a suitable network. The authentication program stored in the unalterable ROM performs an authentication check on the casino game data set at appropriate times, such as prior to commencement of game play, at periodic intervals or upon demand.

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells subdivided into array blocks each including M cell rows and N cell columns. The array blocks are arranged in array block rows and array block columns. Each cell of each cell row of each array block is coupled to an associated one of M word lines. Each cell of each cell column is selectively coupled to develop a data signal transmitted between an associated bit line pair including a primary bit line and a complementary bit line. A row decoder is coupled to provide a corresponding row address signal to each of the M word lines for addressing the cell rows.

Abstract: A method for identifying and selecting pertinent subcircuits from a given circuit design for generating simulation results representative of the given circuit design is disclosed. A large circuit design having a number of input pins and output pins, and one or more clock pins can be simulated by a number of subcircuits where each subcircuit is comprised of circuit information from an input pin to one or more latch devices, an output pin to one or more latch devices, or an output pin to one or more input pins. A latch device can be a flip-flop.

Abstract: An optical multiplexing and demultiplexing device includes: a plurality of optical fibers each terminating in a fiber end for radiating and receiving corresponding light beams; a fiber mounting assembly configured to support the optical fibers so that the fiber ends terminate in substantially the same plane, the mounting assembly also being configured to position the fibers in a regular array of N rows and M columns; reflecting means for reflecting beams radiating from the fiber ends; lens means for collimating and focusing beams propagating between the fiber ends and the reflecting means, the lens means having a focal length associated therewith; and diffraction means for diffracting beams propagating between the lens means and the reflecting means. The reflecting means includes a plurality of N reflective elements, each of the N reflective elements being associated with a corresponding one of the N rows.

Abstract: The electronic casino gaming system consists of several system components, including a microprocessor (12), a main memory unit (13) that is typically a random access memory, and a system boot ROM (14). Also included in the electronic casino gaming system are a non-volatile RAM (17), a mass storage unit (18), a disk subsystem (19), and a PCI bus (20). The disk subsystem (19) preferably supports SCSI-2 with options of fast and wide. A video subsystem (22) is also included in the electronic casino gaming system and is coupled to the PCI bus (20) to provide full color still images and MPEG movies.

Abstract: Method and apparatus for providing authenticated, secure, on-line communication between remote locations including a user terminal adapted to enable a player in one location to remotely communicate via a communications medium such as the Internet with a gaming host in another location. Location of the remote user terminal, the host server and universal time are determined using means for accessing signals generated by geostationary navigational transmitters, such as in the global positioning satellite (GPS) system. Player authentication (identity verification) is determined by use of a personal identification number (PIN) and an electronic signature verification service. Security of communication is accomplished through use of a public-key/private-key encryption system.

Abstract: A method for determining cleaning action on medical instruments and other objects is disclose. The method uses a predetermined soiling substance, for example fresh blood mixed with a radioactive marker. The soiling substance is applied to the instrument as a predetermined contamination. By making various radiation and time measurements one can determine in absolute mass units either the remaining soiling after the completion of a cleaning process or the soiling prior to the cleaning process. By comparing the determined masses one may validate specific cleaning processes, machines or agents.

Abstract: A compact, low current flash EPROM cell that is scaleable to dee-submicron levels for future generations of flash memory arrays is disclosed. This flash memory cell can be fabricated using a twelve masks, triple-poly, salicided process. Source-side injection for programming and poly-to-poly erasing demand very little current and power and such demand can easily be met by charge pump techniques. A select gate in series with the cell channel guarantees enhancement threshold and its sell-alignment and constant channel length will give uniform electrical characteristics in every respect. A virtual ground array fabricated using a self-aligned salicidation process provides a compact cell with high access speed. The cell area is approximately 3F.times.2F where F is a given minimum dimension.

Abstract: A spring-assist drive for a pedal-operated rider-propelled vehicle such as a bicycle which makes use of a wind-up coil spring mounted within the frame of the bicycle as auxiliary power. The spring is selectively wound by the rider operating the pedals to turn a spindle on which is mounted a sprocket wheel. A chain from the sprocket wheel drives a pivoting gear assembly comprising a ratcheting sprocket and attached drive gear. In a preferred embodiment, the tension on the chain will be adjustable by a chain tension adjustment mechanism. The drive gear releasably engages a power gear mounted on a common hub with the spring. A brake band and drum assembly holds the energy in the spring until the brake is released by the rider, whereupon the spring unwinds to drive a sprocket wheel mounted on the common hub, which sprocket wheel is connected to a sprocket wheel mounted on the spindle, turning the rear wheel drive sprocket wheel and the rear wheel.

Abstract: Circuits and methods are provided for operating a transistor as rectifier based upon the detected Vds of the transistor. In sensing the Vds voltage of the SRMOS, during positive conduction, the SRMOS body diode will conduct and the Vds of the SRMOS becomes that of a forward body diode voltage, which may, depending on the type of the device, be approximately -0.6V. If this voltage level is sensed, it may indicates that the SRMOS is turned off too early. During reverse conduction, Vds is non-existent (which is similar to a diode). In this case, the SRMOS may be turned off too late. Thus, by examining Vds, the SRMOS can be operated in such a manner so that it is turned off at an optimal point in time.

Abstract: A secondary subcircuit of a converter circuit is disclosed where a method and circuit for operating a transistor to prevent reverse conduction of the current in the secondary subcircuit is disclosed. The diode in the secondary subcircuits of the prior art is replaced by a transistor and the circuitry for controlling the transistor is made part of the control circuit (ASIC). The secondary converter subcircuit includes a secondary coil for generating a voltage that passes through a first transistor M1, a capacitor, and a second transistor M2, where the output terminal of the subcircuit is across said capacitor. A presently preferred embodiment of a control circuit detects the voltage level at a sync node and the output voltage level at the output terminal and controls transistors M1 and M2 accordingly in generating the desired voltage level at the output terminal.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.

Abstract: Method and apparatus for laser texturing a magnetic recording disk substrate, including a disk-loading and unloading conveyer, a pair of disk-carrying spindles and associated laser systems disposed in spaced-apart relationship, and a disk-handling mechanism disposed between the conveyer and the set of spindles and operative to obtain a first disk rom the conveyer, place it on a first spindle for texturing on one side, remove the partially textured first disk from the first spindle, flip it upside down and place it on a second spindle for texturing on the other side, while at the same time obtaining a second disk from the conveyor and loading it onto the first spindle for texturing on one side. A third disk is then removed from the conveyor and loaded onto the first spindle as the second disk is removed therefrom, flipped over and placed on the second spindle as the first disk is removed therefrom and returned to the conveyor.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.

Abstract: A method for fabricating a split gate memory cell using the self-alignment technique to reduce the amount of misalignment is disclosed. The memory cell generally comprises a floating gate for storing a charge, a select gate for selecting one or more memory cell to operate thereon, a control gate, a buried source region and a buried drain region. Due to the structure of the memory cell, there is no read disturbance when reading the memory cell and its low voltage requirement makes it suitable for low voltage applications. When placed in a memory array, each of the memory cells in the array can be individually programmed or read. In performing the erase operation, a column of information is erased.

Abstract: An insecticide spray apparatus (5) for spraying insecticide in confined areas. The insecticide spray apparatus (5) has a spray gun (10) and a compressor assembly (14) for providing compressed air through a flow line (12) to the spray gun (10). A nozzle (36) atomizes the insecticide for fogging operations and a trigger (34) on the spray gun (10) provides on and off control of the spray action. The compressor assembly (14) has a base (22) with a handle (28) such that the compressor assembly (14) can be carried in one hand by the user. A plurality of bottle holders (24) are provided on the base (22) for carrying spare pesticide containers (30).

Abstract: A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.