Abstract: Software is customized by generating, for a first set of software objects having usage characteristic data collected, a second set of software objects to totally or partially replace the first set of software objects. The second set of software objects is generated based at least in part on the collected usage characteristic data of the first set of software objects. In one embodiment, the generation includes optimizing the second set of software objects being generated based on the usage characteristic data, which include calling frequencies of caller/callee objects of the first set of software objects. In one embodiment, the generation is automatically performed at idle periods of the user's system, if the usage characteristics are determined to be sufficiently changed.

Abstract: A method to optimize differential pairs, based on timing constraints, includes recognizing that two separate traces form a differential pair, and combining sections of the differential pair into one or more trunks. Then, a propagation delay is determined over the differential pair. The determined propagation delay is compared to a timing constraint for the differential pair. If the timing constraint is not met, a length of one or more of the trunks is adjusted and the propagation delay is redetermined and compared to the timing constraint. If the timing constraint is still not met, the process is repeated until the timing constraint is met or until the timing constraint cannot be met. If the timing constraint is eventually met, the one or more trunks are used to produce an adjusted differential pair.

Abstract: Register transfer level (RTL) source code is synthesized to generate a gate-level representation and to generate instrumentation logic corresponding to one or more statements in the RTL source code. The instrumentation logic comprises logic circuitry in addition to that of the gate-level representation. The instrumentation logic indicates an execution status for the corresponding RTL statement(s) during gate-level simulation.

Abstract: An EDA tool is provided with a placement and routing (P&R) module that optimizes placement and routing of an IC design in an interconnect delay driven manner. The P&R module systematically determines if it can improve (i.e. reduce) interconnect delay of the current critical interconnect routing path by determining if it can improve the interconnect delays of its constituting segments, each interconnecting two pins through a component. For each segment, the P&R module determines if the interconnect delay can be achieved by using different interconnect routing path interconnecting the two pins through the component replaced at a different location, and alternatively, through a logically equivalent component disposed at a different location.

Abstract: An electronic design is created through a machine implemented method that includes evolutionarily generating candidate architectures for the electronic design, with the evolutionary generation of the candidate architectures being periodically guided by the designer, and generating an implementation specification for the design in accordance with a selected one of the evolutionarily generated candidate architectures. In one embodiment, the candidate architectures are evolutionarily generated on different abstraction levels, and the generated candidate architectures on the different abstraction levels may be selectively regenerated as often as desired by the designer. In one embodiment, the periodic guidance includes periodic modification of the constraints on the electronic design. In one embodiment, the method further includes facilitating periodic exploration of the electronic design, including the generated candidate architectures, by the designer, to aid the designer in formulating his/her guidance.

Abstract: An apparatus comprising a storage medium having stored therein a plurality of programming instructions and an execution unit is presented. The execution unit, coupled to the storage medium, executes the plurality of programming instructions to implement a hierarchy of collaboration services enabling collaboration between a client computer and a collaboration partner, including a service to determine the system attributes of the client computer and to select an appropriate collaboration service from the hierarchy of collaboration services commensurate with the determined system attributes of the client computer and enabling a collaboration session between the client computer and the collaboration partner.

Abstract: An apparatus is comprised of a storage medium having stored therein a plurality of programming instructions for implementing a set of communication services for establishing and supporting a direct quality voice call to a public switched telephone network (PSTN) extension, and an execution unit, coupled to the storage medium, for executing the plurality of programming instructions. In particular, the set of communication services include services for establishing and facilitating the voice call to the PSTN extension on behalf of the client computer, and services for causing a direct connection to be established between the client computer and the apparatus.

Abstract: An EDA tool is provided with an OPC module that performs optical and/or process pre-compensations on an IC mask layout in a streamlined manner, reusing determined corrections for a first area on a second area, when the second area is determined to be equivalent to the first area for OPC purposes. The OPC module performs the correction on the IC mask layout on an area-by-area basis, and the corrections are determined iteratively using model-based simulations, which in one embodiment, include resist model-based simulations as well as optical model-based simulations.

Abstract: An apparatus is programmed to automatically remove timing hazards from a circuit design. The apparatus identifies certain level sensitive storage circuit elements in the circuit design. The identified level sensitive storage circuit elements are those having timing hazards. The timing hazards arise as a result of potential skews between the reference signal for the circuit design and the synchronization signal controlling each storage circuit element. A skew, introduced by a gated or divided clock, cannot be assured to be within a design tolerance limit. Therefore, the program enables the apparatus to transform the identified level sensitive storage circuit elements into level sensitive storage circuit elements controlled by synchronization signals that do not have potential skews with respect to the reference signal of the circuit design. The transformation, however, is accomplished without altering the functionality of the circuit design.

Abstract: Advertisement consumption activities of a user are monitored. The user is credited with telephony service credits in accordance with observed advertisement consumption activities. In turn, telephony service for the user is facilitated. The facilitation is based at least in part on the amount of telephony service credits credited to the user.

Abstract: The present invention beneficially provides a method and apparatus for cross-referencing graphical objects and hardware description language (HDL) statements. According to one aspect of the present invention, a cross-referencing record is automatically generated to map graphical objects to corresponding HDL statements. According to a second aspect of the invention, a request is received to cross-reference a HDL statement and a graphical object. Based on the request, the cross-referencing record is accessed to identify a target of the request.

Abstract: A novel air/asthma advice method and apparatus for providing air/asthma advice to an asthma patient, taking into consideration indoor allergen as well as outdoor air quality conditions, is disclosed. Allergen data (preferably for allergen with sizes smaller than 5 micron) for an indoor location (where the asthma patient is situated) are collected, and provided to a geographically removed air/asthma advice server. The server, in turn, retrieves air quality data for a surrounding outdoor area of the indoor location (from either a private or an independent source), and generates an allergen advice response for the asthma patient. The air/asthma advice is generated based at least in part on the received allergen data and the retrieved air quality data. The air/asthma advice may be delivered to the asthma patient in any one of a number of forms (a beeping alert, a pager, fax, email or voice message, and so forth). Various other alterations and modifications under different embodiments are also disclosed.

Abstract: A method and apparatus for maintaining design information corresponding to a design. In one embodiment, an electronic notebook for maintaining design information maintains information corresponding to a design, and follows the steps of receiving a request to add note information corresponding to the design, and automatically copying, in response to the request, at least a portion of the design to a note of the electronic notebook. As a result, detailed design information such as, but not limited to, design intent and design history is maintained throughout the development and manufacturing of the design, as well as other information if desired, for the design.

Abstract: An EDA tool is provided with a floorplan generator to automatically generate an optimized floorplan for an IC design having a number of design blocks. The floorplanner generates an initial O-tree representation for the design blocks. The floorplanner then perturbs the O-tree representation to seek an alternate O-tree representation that represents an optimized placement of the design blocks in accordance with a cost function. The floorplanner performs the perturbation systematically for all design blocks, traversing the O-tree representation in a depth-first manner and removing one design block at a time. In one embodiment, for each removed design block, the floorplanner also seeks an appropriate re-insertion point for the removed design block systematically by traversing a reduced version of the O-tree representation augmented with candidate insertion points in a depth-first manner.

Abstract: An integrated circuit is described as comprising a plurality of logic elements (LEs), each of which having a plurality of outputs, and a partial scan register. The plurality of LEs are operative to generate a plurality of output signals in response to a plurality of input signals correspondingly applied to the LEs. The partial scan register is reconfigurably coupled to select ones of the LEs such that, when enabled, the partial scan register is operative to capture and output on a scan bus a record of signal state values circuit elements emulated by the selected LEs in a particular clock cycle of an operating clock, wherein the partial scan register is enabled with application of a scan clock appropriately scaled to the operating clock.

Abstract: The present invention beneficially provides an improved method and apparatus for designing submicron integrated circuits. A tag identifier is provided to an integrated circuit (IC) design. The tag identifier defines properties for edge fragments in the IC design having edge placement distortion due to the proximity of neighboring features. Edge fragments are tagged if they have the properties defined by the tag identifier. Arbitrary assist features are introduced for each tagged edge fragment. Model-based optical and process correction (OPC) is performed on the tagged edge fragments and the corresponding assist features.

Abstract: A parasitic extraction tool (PEX) is provided to generate electrical modeling data for an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The PEX includes a read function for reading extracted connectivity and geometrical data of various layout cell hierarchies of the IC design, that are organized and indexed by layout nets. The PEX also includes a write function for writing generated electrical modeling data into a parasitic database (PDB), which is physically organized to accommodate physical storage of the electrical modeling data in multiple physical media, and concurrent usage of the electrical data by multiple client applications, e.g. post layout analysis tool. In one embodiment, the PDB further includes an application interface that shields the physical organization of the PDB, and a logical abstraction of the physical organization to facilitate implementation of the application interface.