Abstract: The milling and whipstock assembly includes a whipstock having a ramp portion for directing the milling assembly to cut a secondary borehole in an existing cased borehole. The milling assembly includes a shaft having rigid and flexible portions and an under gauge cutting tool disposed on the lower end of the flexible portion and a full gauge cutting tool disposed on the rigid portion. A third under gauge cutting tool is disposed on the flexible portion in between the full gauge and under gauge cutting tools. In operation, the milling and whipstock assembly is lowered into the borehole and then the milling assembly is detached from the whipstock assembly. As weight is placed on the milling assembly, the ramp portion places a side load on the lower under gauge cutting tool causing the flexible portion of the shaft to flex and pivot allowing the under gauge cutting tool to come into engagement with the wall of the casing allowing the under gauge cutting tools to cut a window in the cased borehole.

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus.

Abstract: A system and method for the streamlined execution of complex or repeating instructions. The method comprises creating a specialized instruction unit for executing a group of operations and then executing the group as they appear in an instruction stream. The system includes a programmable specialized instruction unit for executing the group of instructions as they appear in an instruction stream. The method comprises receiving a plurality of instructions, examining the plurality of instructions, identifying a subset of the plurality of instructions, creating a specialized instruction unit which is operable to execute the subset, and executing the subset in the special instruction unit upon an occurrence of the subset. Examining the plurality of instructions may occur at such times as compiling a computer program, performing an initialization procedure, or fetching or decoding instructions before execution.

Abstract: A microprocessor includes an instruction cache having a cache access time greater than the clock cycle time employed by the microprocessor. The instruction cache is banked, and access to alternate banks is pipelined. The microprocessor also includes a branch prediction unit. The branch prediction unit provides a branch prediction in response to each fetch address. The branch prediction predicts a non-consecutive instruction block within the instruction stream being executed by the microprocessor. Access to the consecutive instruction block is initiated prior to completing access to a current instruction block. Therefore, a branch prediction for the consecutive instruction block is produced as a result of fetching a prior instruction block. A branch prediction produced as a result of fetching the current instruction block predicts the non-consecutive instruction block, and the fetch address of the non-consecutive instruction block is provided to the instruction cache access pipeline.

Abstract: A surgical cable system and method for securing surgical cable around a portion of a human element (e.g., bone) are described. The surgical cable system may include an eyelet. The eyelet may be configured to be positionable within a cable opening formed in a portion of the bone, such that the cable may pass through the eyelet when the cable is inserted into the cable opening. The eyelet may prevent the cable from contacting the bone portion proximate the cable opening, thus protecting the bone portion from damage due to, e.g., friction from motion of the cable against the bone portion. In an embodiment, the eyelet includes a single eyelet member. In an alternative embodiment, the eyelet includes an eyelet member and at least one endpiece connectable to the eyelet member. In an alternative embodiment, the eyelet includes two eyelet members. The two eyelet members may be configurable to form a fixable engagement.

Abstract: A memory-efficient system and method for generating data blocks "on demand" for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator.

Abstract: An improved system and method for transferring data over a serial bus. Incoming data is stored into data buffers with a dynamically variable size. The size of each data buffer may be adjusted as new data come in. Data with the same originating address are stored in the same data buffer. An arbiter, coupled to the data buffers and to the serial bus, monitors each of the data buffers and the availability of the serial bus. When the serial is available, the arbiter transfers data from one of the data buffers according to some predetermined priority. For example, the largest buffer may have the highest priority. Such an assignment of priority makes very efficient use of the serial bus since larger amounts of data have less overhead and are thus more efficient to transfer. In addition, while data is transferring out of one of the data buffers, data is accumulating in all the other buffers. This makes the other buffers larger and more efficient to transfer upon later availability of the serial bus.

Abstract: An integrated circuit which includes a temperature modeling circuit for reducing operational activity of the integrated circuit when its operating temperature exceeds a predefined threshold. The temperature modeling circuit includes several multiplexers each of which corresponds to a particular sub-circuit within the integrated circuit. The multiplexers select one of at least two heat generation values inputted thereto in accordance with the operating mode of the corresponding sub-circuit. A multi-input adder adds the selected heat generation values along with values representing the rate at which heat is being dissipated by the integrated circuit, the rate at which heat is being generated by background operations of the integrated circuit, and a previous temperature of the integrated circuit. The added values relate to the current operating temperature of the integrated circuit which is compared to a predefined temperature using a comparator.

Abstract: In preferred embodiments described herein, a transducer head is affixed to the lower end of a wireline borne scanner sub for rotation thereby. The transducer head includes a pair of transducers which may be adjusted radially inward or outward with respect to the head so that optimum standoff may be achieved without the need for numerous transducer heads of various sizes. In a described exemplary embodiment, the transducers are adjusted by means of an indexing system which permits fine control over the amount of adjustment for the transducers.

Abstract: A data acquisition system comprising a Configuration Manager for intelligently managing access to DAQ configuration information. The data acquisition system comprises a computer system coupled to a data acquisition device, a data acquisition application (user application) executing on the computer system, and DAQ driver level software executing on the computer system. The memory of the computer system stores a hardware database which includes information on DAQ objects in the DAQ system, and the memory stores configuration files which comprise desired configurations of the DAQ system. The Configuration Manager of the present invention executes in the computer system to control access to the hardware database and configuration files stored in the computer system. The present invention also includes a method for providing access to information on data acquisition (DAQ) objects in the DAQ system.

Abstract: An integrated circuit comprising a plurality of reconfigurable logic networks, one or more buffers, a configuration control network, and an embedded processor, all comprised as an integral part of the integrated circuit, and a method of operation of the integrated circuit. One or more of the buffers are coupled between two of the plurality of reconfigurable logic networks. The buffers isolate the plurality of reconfigurable logic networks from one another. The integration control network is coupled to each of the plurality of reconfigurable logic networks, and may also be coupled to one or more buffers. The embedded processor is operable to reconfigure one or more of the plurality of reconfigurable logic networks over the configuration control network. The integrated circuit may also comprise a local memory. The local memory is coupled to the embedded processor, and is operable to store data and/or instructions accessible by the embedded processor.

Abstract: In general, in one aspect, the invention features a system for operating the computer in any of at least two different interactive modes, along with a switch having at least two states. An access control device allows a user to change the state of the switch, for changing which interactive mode is currently active.

Abstract: A main memory comprises one or more memory devices which include logic for performing a predetermined graphics operation upon graphics primitives stored therein. The microprocessor(s) within the computer system may direct the memory to perform the predetermined operation upon the graphics primitives instead of performing the operation within the microprocessor(s). If the graphics primitives are stored into multiple memory devices, each memory device operates upon the graphics primitives stored within that memory device in parallel with the other memory device's operation. Accordingly, the bandwidth is a linear factor of the number of memory devices storing graphics primitives. In one embodiment, each memory device iteratively performs the predetermined operation upon the set of graphics primitives stored in that memory device. Because the memory device is iterative, logic for performing the predetermined graphics operation upon one graphics primitive at a time may be employed.

Abstract: A modular distributed I/O system includes a computer coupled to module banks through a network bus. A module bank includes a communication module, terminal bases, and I/O modules. The adjoined terminal bases form a local bus mastered by the communication module. The I/O modules connect to the local bus through terminal bases. I/O modules are pluriform and programmable. The communication module maintains a memory image of the configuration state of each I/O module resident in the module bank. A memory image persists when an I/O module is removed from its terminal base. The memory image is used to configure a new I/O module which is inserted into the same terminal base. The communication module monitors for communication failure on the network bus, and is configured to capture the state of the module bank and automatically restore this captured state after a power-loss event. The terminal bases realize a local bus which includes a parallel bus, a serial bus, and an address assignment bus.

Abstract: An apparatus for accelerating move operations includes a lookahead unit which detects move instructions prior to the execution of the move instructions (e.g. upon selection of the move operations for dispatch within a processor). Upon detecting a move instruction, the lookahead unit signals a register rename unit, which reassigns the rename register associated with the source register to the destination register. In one particular embodiment, the lookahead unit attempts to accelerate moves from a base pointer register to a stack pointer register (and vice versa). An embodiment of the lookahead unit generates lookahead values for the stack pointer register by maintaining cumulative effects of the increments and decrements of previously dispatched instructions. The cumulative effects of the increments and decrements prior to a particular instruction may be added to a previously generated value of the stack pointer register to generate a lookahead value for that particular instruction.

Abstract: An execution unit configured to execute vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far data path is configured to handle effective addition operations, as well as effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close data path includes an adder unit configured to generate a first and second output value. The first output value is equal to the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. The two output values are conveyed to a multiplexer unit, which selects one of the output values as a preliminary subtraction result based on a final selection signal received from a selection unit.

Abstract: A computer system includes an I/O controller and a bridge logic device which transmit status data via a serial bus. The I/O controller comprises an embedded controller, a memory device, and a serial bus interface including a transceiver, a transmit register, and a receiver register. The bridge logic also includes a serial bus interface with a transceiver, a transmit register, and a receiver register. Data is transmitted from the transmit register of one device to the receive register of the other device. Although the serial bus protocol limits data transfers to eight-bit segments, the I/O controller and bridge logic transmit up to twenty-four different variables by encoding each transmitted byte into a data frame that includes a two-bit frame identifier and a six-bit data field. Further, one of the data frames transmitted by the I/O controller includes an acknowledge bit to indicate when a previous frame has been received from the bridge logic.

Abstract: Method and apparatus for computer-aided assessment of organizational process or system. Method and apparatus are adapted to display computer displayed questions to an assessor, who then inputs numerical inputs relative to the assessor's perception of the process or system. Filtering techniques inhibit entry of unsupported numerical inputs which may be untrue and/or exaggerated. Sequential questions used in combination provide more accurate assessment of the system or process, thereby enabling focused audits and/or inspections.

Abstract: A process for the mass production of computers where software is automatically installed according to configure-to-order requirements. Additionally, the process captures the as-built hardware and software components of each computer for the vendor service and support program. Furthermore, the process provides a software installation environment which is secure from any undetectable alteration and offers control and auditing of subcontractors who produce systems according to manufacturer's specifications. Finally, the process automates the tracking and reporting of royalty payments to the appropriate recipient.

Abstract: A microprocessor configured to store predecode information that is removed from an instruction cache is disclosed. In one embodiment, the microprocessor comprises a predecode unit and an instruction cache. The predecode unit is configured to receive instruction bytes from a level two cache and generate corresponding predecode information. The instruction cache is coupled to the predecode unit and comprises two pluralities of storage locations, one for storing instruction bytes and a second for storing predecode information corresponding to the instruction bytes. The instruction cache is configured to receive and store the instruction bytes and predecode information from the predecode unit. The instruction cache is also configured to output at least part of the corresponding predecode information for storage in the level two cache when the instruction bytes and corresponding predecode information are replaced in the instruction cache.