Abstract: A stent comprising a coil including a plurality of arcuate sections that alternate directions around a central axis, each arcuate section including a pair of curved turns joined by a cusp, and the cusps of adjacent arcuate sections intermeshing and defining at least one region of overlap, which in turn describes a helix around and along the length of the coil. In the preferred embodiment, there are two regions of overlap, which together describe a double helix. In another preferred embodiment, the stent is bifurcated so as to support a branched vessel or the like.A method for forming a stent, including the steps of providing a flat sheet of material, chemically etching said sheet to form a blank, and forming said blank into a cylindrical coil. The coiling step is preferably carried out on a plurality of rollers.

Abstract: A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predicted-taken), or the sequential index (if predicted not-taken) is provided as the index to the instruction cache. The selected physical tag is provided to a reverse translation lookaside buffer (TLB) which translates the physical tag to a virtual page number. Concatenating the virtual page number to the virtual index from the instruction cache (and the offset portion, generated from the branch prediction) results in the branch target address being generated. In one embodiment, a current page register stores the most recently translated virtual page number and the corresponding real page number.

Abstract: A data prediction structure is provided for a superscalar microprocessor. The data prediction structure stores base addresses and stride values in a prediction array. The base address and the stride value from a location within the data prediction structure indexed by an instruction address are added to form a data prediction address which is then used to fetch data bytes into a reservation station storing an associated instruction. If the data associated with an operand address calculated by an associated functional unit resides in the reservation station, the clock cycles used to perform the load operation have occurred before the instruction reached the reservation station. Additionally, the base address is updated to the address generated by executing an instruction each time the instruction is executed, and the stride value is updated when the data prediction address is found to be incorrect.

Abstract: A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predicted-taken, or the sequential index if predicted not-taken) is provided as the index to the instruction cache. The selected physical tag is provided to a reverse translation lookaside buffer (TLB) which translates the physical tag to a virtual page number. Concatenating the virtual page number to the virtual index from the instruction cache (and the offset portion, generated from the branch prediction) results in the branch target address being generated. In one embodiment, the process of reading an index from the branch prediction storage, accessing the instruction cache, selecting the physical tag, and reverse translating the physical tag to achieve a virtual page number may require more than a clock cycle to complete.

Abstract: An apparatus and method are presented for performing a wafer fabrication operation upon each of a plurality of semiconductor wafers which facilitate determination of a source of semiconductor wafer contaminants or defects. A wafer fabrication tool of the present invention includes a process chamber for processing a semiconductor wafer and a wafer handling system for transporting the semiconductor wafer between a wafer cassette and the process chamber. Semiconductor wafers contained within the wafer cassette are assigned numbers and processed one after another in a predetermined order. The wafer handling system is configurable to remove semiconductor wafers from the wafer cassette for processing in the predetermined order. One embodiment of the wafer handling system includes a mechanical hand for gripping a semiconductor wafer and a mechanical arm coupled to the mechanical hand for positioning the mechanical hand.

Abstract: An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register.

Abstract: A dynamic memory allocation routine maintains an allocation size cache which records the address of a most recently allocated memory block for each different size of memory block that has been allocated. Upon receiving a dynamic memory allocation request, the dynamic memory allocation routine determines if the requested size is equal to one of the sizes recorded in the allocation size cache. If a matching size is found, the dynamic memory allocation routine attempts to allocate a memory block contiguous to the most recently allocated memory block of that matching size. If the contiguous memory block has been allocated to another memory block, the dynamic memory allocation routine attempts to reserve a reserved memory block having a size which is a predetermined multiple of the requested size. The requested memory block is then allocated at the beginning of the reserved memory block.

Abstract: A system and method for controlling relays. The method may comprise receiving one or more input commands for a plurality of relays, with the plurality of relays including a first relay, and a last relay, initiating actuation of the first relay after receiving the input relay commands, and initiating actuation of the last relay after initiating actuation of the first relay. Initiating actuation of the last relay does not wait for a debounce of the first relay. The method waits a debounce period after initiating actuation of the last relay. The debounce period operates to debounce the last relay and the first relay. One or more second relays may also be included in the debounce sequence. The relays may be latching or non-latching relays. The method may determine if another relay is required to be actuated after initiating actuation of each relay. One of the input commands may include a debounce mode input. A delayed debounce mode debounces the plurality of relays only after the last relay has been actuated.

Abstract: The invention is a computer interface with a hardwired button array on the computer chassis for simulating the apparatus of common consumer electronic devices. Each button of the array of buttons is connected to at least two wires, with the depression of a button causing an electrical connection between the corresponding two wires. The voltage on one of these wires is forced to a steady-state logic low, while the voltage on the other wire is allowed to float electrically free. Nonetheless, the second wire is at a steady-state high voltage due to that wire's connection through a pull-up resistor to a voltage source. Upon electrical connection, the wire that is floating free acquires a logic low voltage. In response, a line state detector sends an interrupt signal to a microprocessor, which transitions the voltage on the wires forced to a steady-state logic low from a logic low to a free floating state.

Abstract: An apparatus for performing balloon angioplasty and stent deployment in a vessel having a narrowed portion, including: a stent deployment member having an inner core and a stent, the inner core having a first lumen therethrough and proximal and distal ends, with the stent being releasably supported on the inner core, and an angioplasty balloon having a sealable distal end and an open proximal end, the proximal end being sealed to the inner core such that the balloon can be inflated by the passage of a fluid through the first lumen. Also disclosed is a method for widening a narrowed portion of a vessel, including: providing a balloon adjacent a stent on a single catheter, introducing a balloon at the narrowed portion, inflating the balloon, deflating the balloon, advancing the balloon beyond the narrowed portion, deploying the stent, and withdrawing the deflated balloon through the deployed stent.

Abstract: An apparatus and method for write posting in a universal serial bus (USB) system includes a host computer connected to USB devices via a USB. The host computer generates requests to write data to memory within the USB device. The host computer includes a queue for posting the write requests on generation thereof. The write requests are posted in the queue until the host computer transmits a single data packet generated from the posted write requests. The Data packet is generated in response to the host computer generating a request to read data from the USB device, the host computer determining that the most recently posted write request is directed to a memory location within the USB device which is nonpostable, or an indication that the queue lacks storage space for subsequent write requests. The USB device receives the transmitted Data packet from the host computer and writes data to internal memory locations in accordance with the received Data packet.

Abstract: A carrier-recovery loop for a receiver in a communication system with features that facilitate initialization of the loop. The carrier-recovery loop is a PLL that uses a feedback signal to keep a recovery oscillator phase-locked to the carrier of a received signal. In the present invention, an initializing value of the feedback signal is stored in a memory and provided to a digitally controlled recovery oscillator (DCO). This initializing value brings the recovered signal to an initial frequency that approximates the carrier frequency. When the receivers starts to acquire a phase-lock with the carrier, the carrier-recovery loop is in a condition close to the desired phase lock. Preparing the DCO in this manner imparts a significant improvement to the carrier-recovery loop. The response time for the loop to acquire a phase lock depends in part on its initial frequency offset from the carrier. In general, reducing this initial offset reduces the loop's acquisition time.

Abstract: A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The video controller is further used for transmitting screen images to a remote computer system to facilitate system failure analysis. A plurality of system management remote units are provided for coupling to various components and busses within the host computer system.

Abstract: A computer system includes a South bridge logic device that monitors the FLUSHREQ signal and masks that signal when the CPU transitions the computer to a low power mode of operation. Once masked, the FLUSHREQ cannot be asserted to the North bridge and the conflict between attempts by the CPU and an ISA device to run cycles on the PCI bus is avoided. The South bridge also masks all requests to run cycles on the PCI bus that are not originated by the CPU. The South bridge includes a programmable control register and a PCI arbiter. When a control bit is set in the register, the PCI arbiter waits for FLUSHREQ to be deasserted and then masks FLUSHREQ. The PCI arbiter preferably also disables PCI arbitration by masking all non-CPU. Only the CPU can run PCI cycles when the non-CPU requests are masked. The programmable control register also includes a masking status bit that is set when both the FLUSHREQ and non-CPU request signals are masked by a request mask state machine.

Abstract: A graphics controller (IMC) which performs pointer-based and/or display list-based video refresh operations that enable screen refresh data to be assembled on a per window or per object basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains pointers to various buffers in system memory comprising video or graphics display information. The graphics controller manipulates respective object information workspace memory areas corresponding to each object or window, wherein the workspace areas specify data types, color depths, 3D depth values, alpha blending information, screen position, etc. for the respective window or object on the screen. Each workspace area also includes static and dynamic pointers which point to the location in system memory where the pixel data for the respective window or object is stored.

Abstract: In a semiconductor employing shall trench isolation, a subtrench conductive layer formed before the isolation dielectric is present by implanting dopants into the floor and sidewalls of the shallow trench using a large tilt angle (LTA) implant. The subtrench conductive layer is advantageously used to interconnect what would normally be isolated devices. In lieu of metal or polysilicon interconnects which reside over the isolation dielectric, the subtrench conductive layer is formed entirely within the silicon substrate, and resides beneath and laterally adjacent the isolation dielectric. The conductive layer is formed by implanting ions into the floor and sidewalls of a shallow trench prior to filling the trench with the isolation dielectric. The implantation at specified dosages presents a layer of dopant within the exterior surfaces of the trench sidewalls and floor. Implantation or diffusion of source/drain regions occur after the conductive layer is formed and the isolation dielectric is formed.

Abstract: A chemical vapor deposition system including a chemical vapor deposition chamber, an inlet line for directing reactant gases into the deposition chamber, and outlet line for discharging waste by-product from the deposition chamber, and a detachable trap position along the outlet line for trapping at least a portion of the waste by-product. The trap can include an array of baffles for increasing the surface area within the trap and disrupting flow within the trap. The trap can also include cooling structure for cooling at least a portion of the trap to enhance waste by-product deposition within the trap.

Abstract: A speculative store buffer is speculatively updated in response to speculative store memory operations buffered by a load/store unit in a microprocessor. Instead of performing dependency checking for load memory operations among the store memory operations buffered by the load/store unit, the load/store unit may perform a lookup in the speculative store buffer. If a hit is detected in the speculative store buffer, the speculative state of the memory location is forwarded from the speculative store buffer. The speculative state corresponds to the most recent speculative store memory operation, even if multiple speculative store memory operations are buffered by the load/store unit. Since dependency checking against the memory operation buffers is not performed, the dependency checking limitations as to the size of these buffers may be eliminated.

Abstract: A system and method for auto-polling a status register within a physical layer (PHY) interface to a local area network (LAN). The system includes a host CPU which needs to detect and service interrupts generated by a PHY device on the LAN which is coupled between a first transmission medium (such as copper or fiber cable) and a management interface to the system. The system further includes an auto-polling unit which monitors activity on the management interface of the PHY device. When the auto-polling unit detects a lack of activity on the management interface of the PHY for a predetermined interval, the auto-polling unit reads a first value from the PHY status register. This first status value is then compared to a previously stored value which corresponds to the last PHY status value read by the host CPU. If a mismatch is detected between these two values, an interrupt is generated to the CPU.