Abstract: An improved door closure indicator is provided. The indicator operates on pressure levels read within a pressurized chamber rather than from proximity switches coupled between the chamber and the door. If the door seals to the chamber, pressure within the chamber will quickly change, and the change will be read on a pressure sensor indicative of the door closure. According to one example, the chamber can comprise a vacuum chamber and the pressure sensor can be a vacuum monitor. Once vacuum is detected, it is determined with more absolutism that the door is actually closed rather than having to rely upon switch operation and/or alignment of the door activation mechanism to proximity switches arranged on the chamber housing.

Abstract: A computer system implementing a fault detection and isolation technique that tracks failed physical devices by identification (ID) codes embedded in each component of the computer for which the ability to detect faults and isolate failed devices is disclosed. The computer system comprises one or more CPU's, one or more memory modules, a master control device, such as an I2C master, and a North bridge logic device coupling together the CPU's, memory modules, and master control device. The master control device also connects to the CPU's and memory modules over a serial bus, such as an I2C bus. Each CPU and memory module includes an ID code that uniquely identifies and distinguishes that device from all other devices in the computer system. The computer also includes a non-volatile memory device coupled to the CPU for storing a failed device log which includes a list of ID codes corresponding to failed physical devices.

Abstract: The present invention provides for a method and an apparatus for encoding coherency tag information for a plurality of busses. A first processor bus is coupled to a host controller. A second processor bus is coupled to a host controller. The host controller is coupled to a single coherency tag bank. Coherency tag data from the first processor bus and the second processor bus is stored into the coherency tag bank. A location of a data set sought by the first processor and the second processor is determined using the coherency tag data.

Abstract: Apparatus for making a plastic lens. Apparatus includes a mold cavity and a cooling fluid distributor. The apparatus is adapted to produce a plastic lens from a liquid composition.

Abstract: A secure system and method is provided for remotely waking a computer from a power down state. In one embodiment, a network interface card receives incoming data packets via a network connector. A control module is coupled to the network connector and is configured to search the incoming packets for a wake-up pattern. The control module also verifies that the packet's destination address matches the destination address of the network interface card. If the destination addresses match and a wake-up pattern is found, the control module decrypts an encrypted value from the incoming packet and compares the result to an expected value. A successful comparison causes the control module to assert a signal to wake up the host computer. Preferably, a standard public/private key pair encryption scheme is used, and the source of the data packet encrypts the expected value with a private key.

Abstract: According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which identifies information located in a main memory. The address may also identify one or more other versions of the information located in one or more caches. The process of filling the designated cache with the information is started by locating the information in the main memory and locating other versions of the information identified by the address in the caches. The validity of the information located in the main memory is determined after locating the other versions of the information. The process of filling the designated cache with the information located in the main memory is initiated before determining the validity of the information located in main memory. Thus, the memory reference is speculative.

Abstract: A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.

Abstract: A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or frequency of soft memory errors is provided to control logic in a memory controller, which intelligently modifies the frequency of memory calibration cycles based on the detected memory errors. Thus, in response to an unacceptable number of memory errors, the memory controller may increase the frequency of calibration cycles. The memory controller may include error checking logic that monitors memory errors on multiple memory channels, if multiple memory channel are provided, to enable the memory controller to modify calibration frequency on a channel-by-channel basis.

Abstract: A system and method are presented for sending a message from one telephone to another by transmission of a short code. A set of message units stored within the receiving telephone is assigned to a set of codes which may be transmitted. The receiving telephone is a code-compatible telephone configured to detect an incoming code and forward the corresponding message unit to an output device associated with the code-compatible telephone. A message unit may comprise an entire message, or a portion of a message, such that multiple message units are combined to form a message. The message units may be alphanumeric or non-alphanumeric. An alphanumeric message unit contains multiple alphanumeric characters, while a non-alphanumeric message unit may contain graphical or auditory information. An alphanumeric or graphic message unit is forwarded to a display screen on the code-compatible telephone if the corresponding code is received. An auditory message unit is instead forwarded to the telephone's loudspeaker.

Abstract: The drilling assembly includes an eccentric adjustable diameter blade stabilizer having a housing with a fixed stabilizer blade and a pair of adjustable stabilizer blades. The adjustable stabilizer blades are housed within openings in the stabilizer housing and have inclined surfaces which engage ramps on the housing for camming the blades radially upon their movement axially. The adjustable blades are operatively connected to an extender piston on one end for extending the blades and a return spring at the other end for contracting the blades. The eccentric stabilizer also includes one or more flow tubes through which drilling fluids pass that apply a differential pressure across the stabilizer housing to actuate the extender pistons to move the adjustable stabilizer blades axially upstream to their extended position. The eccentric stabilizer is mounted on a bi-center bit which has an eccentric reamer section and a pilot bit.

Abstract: A generic mounting structure is provided between a hard disk drive (HDD) and a computer. The structure includes a plurality of nubs disposed on a brace that can be fitted onto a HDD. The nubs are preferably cylindrical members having an enlarged diameter head. The computer includes, either internally or externally, a bay having a boot interface that closely receives the nubs. The boot interface includes a tapered slotted recess that closely receives the enlarged diameter head of the nubs. In a preferred embodiment, at least two different computer platforms incorporate a substantially identical bay design. Likewise, a brace having nubs oriented in a manner complementary to the bay design is fitted onto at least two different HDDs. Because the HDDs and computer platforms have common mechanical connection by virtue of the brace and bay designs, the HDDs may be exchanged between these computer platforms. In a different embodiment of the present invention, the nubs may be formed directly onto the HDD itself.

Abstract: A computer system adapted for hot-pluggable components such as memory modules that may be replaced, upgraded and/or added without disturbing normal operation of the computer system. A failing memory module may be replaced by copying its contents to a new memory module in a background operation while the computer system runs its operating system and applications programs. When all contents are copied to the new memory module, the failing memory module may be removed without having to shut down the computer system. Computer system memory may be upgraded or added to by inserting the new memory module(s) into vacant disconnected memory connectors, whereupon the computer system automatically recognizes the new memory module(s), synchronously connects the new memory module(s) to the computer system memory bus, initializes the new memory module(s), and then notifies the operating system that the new memory module(s) is available, all without disturbing normal operation of the computer system.

Abstract: An architecture, system and method are provided for efficiently transferring data across multiple processor buses. Cache coherency is maintained among cache storage locations within one or more of those processors, even in instances where a hit-to-modified condition occurs to those cache storage locations. A guaranteed access is maintained to bus agents operating on a first processor bus so that out-of-order or split transactions are prevented on that bus even under conditions of a hit-to-modified condition. One or more of the other processor buses undergo a defer transaction, yielding an out-of-order condition which is resolved after the initial transaction and a snoop request cycle has been placed upon the first processor bus. The present architecture, system and method thereby prevents live-lock conditions, and does so without automatically deferring each transaction yielding a hit-to-modified signal.

Abstract: A system is disclosed for facilitating operation of a peripheral bus, such as a PCI bus, that operates at multiple clock speeds. The system includes an expansion slot controller that identifies the number of peripheral devices that have been installed in the expansion slots, and further determines whether these devices support high speed operation. The expansion slots transmit a signal indicating the presence of a peripheral device in the slot, and also transmit a signal indicating whether the device is operable at the higher clock frequency. Once the expansion slot controller determines this information, it decides whether operation at the higher frequency is supported by the peripheral devices and by the bus bridge. The expansion slot controller informs each peripheral device of what the operating frequency will be, and transmits a signal to the PCI bus bridge indicating if high frequency operation will be supported.

Abstract: A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to control logic in a memory controller that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices. In addition, the memory controller also monitors the expected remaining life of the memory devices, and the number of errors occurring in the memory devices, and based on these parameters, may change the frequency of the calibration cycles.

Abstract: A transistor fabrication process is provided which derives a benefit from having an asymmetrical LDD structure. A silicon-based substrate is provided. A gate oxide layer is grown across the substrate. The gate oxide layer may be incorporated with barrier atoms bonded to silicon or oxygen atoms. Suitable barrier atoms include nitrogen atoms which help reduce hot electron effects by blocking diffusion avenues of carriers (i.e., holes or electrons) from the drain-side junction, through the channel near the drain and into the gate oxide of the ensuing transistor. A polysilicon layer is then deposited across the gate oxide layer. Portions of the polysilicon layer and the oxide layer are then removed to form a gate conductor and gate oxide and to expose source-side and drain-side junctions within the substrate. A first dopant is implanted exclusively into only the source-side junction region. A second implant is then forwarded at a lower concentration into both junctions.

Abstract: The present invention is related to a cable coupling system for supplying DC power in rack-mounted server systems. The cable coupling system involves grouping related power supply and power return cables and placing ends of those cables in a cable-end housing. Electrically contacting the ends of the cables takes place through apertures in the back surface of the cable-end housing and corresponding electrical contact pins on a connection area of the rack-mounted system. The system also includes a connection guide having a lip that insures that the cable-end housing only connects to the electrical contact pins in one direction, thereby insuring that the polarity is not reversed in the supply of DC power. Further, the lip portion of the connection guide, in combination with a pry aperture on the top of the cable-end housing, assists removal of the cable-end housing by providing locations whereby a screw driver or other mechanism can be used to pry the cable-end housing.

Abstract: Architecture, circuitry, and methods are provided for producing a content addressable memory (CAM). The CAM includes one or more CAM cells arranged in an array. Each CAM cell is symmetrical about its x- and y-axis to form rows and columns of the array. Additionally, each CAM cell can use either SRAM or DRAM storage cells implemented in either a binary or ternary arrangement. If the CAM cell is a ternary SRAM design, then the cell size is no more than 4 microns by 1-½ microns, assuming a 0.15 micron critical dimension. Critical dimension is noted as the smallest resolvable size for the particular process being employed. The CAM cell utilizes a selection circuitry that will disable the compare circuit during times when a compare operation is not being performed. This will ensure the compare circuit will not consume power during, for example, a read or write operation.