Abstract: A new post-processing methodology reduces the unwanted noise artifacts present in the output images of DCT-based compressed signals. The method determines noise intensity in the region of each pixel of an image and filters each pixel corresponding to this noise intensity. This noise intensity includes ringing intensity and block noise intensity. Determining the noise intensity includes calculating a short range power spectrum and a long range power spectrum. A spectrum is identified as ringing if the short range power spectrum is negative and the long range long range power spectrum is positive. A spectrum is identified as block noise if the short range autocorrelation coefficient is positive and the long range autocorrelation coefficient is positive.

Abstract: An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.

Abstract: The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum versatility and configurability using switched resources in the form of configurable crossbar switches.

Abstract: During a trace the timing stream has the active and stall information, PC stream has all the discontinuity information, and the data stream has all the data log information. The various streams are synchronized using markers called sync points. The sync points provide a unique identifier field and a context to the data that will follow it. After data corruption a sync point is inserted into the data stream. The ID of this sync point may repeat a previous sync point ID.

Abstract: Code will switch to secure code via an exception only. All PC and data trace will be turned off during secure code. This will occur regardless of trace being in standard trace mode or event profiling mode. Timing, if on, will switch to standby mode. On return from the secure code, the switches that were already on will switch back and turn on. The address reported in the end sync point will be the address 0x01. Since this is an illegal address, this information is sufficient to indicate an end sync point was caused in secure code.

Abstract: Current generation digital media processors support multi-format video resolutions, SDTV, Progressive Scan and HDTV. Built-in video encoders directly support NTSC and progressive 480P video outputs. These two video formats have different image bandwidth and output gain requirements, but are normally filtered by fixed bandwidth filters. This invention provides adjustable filter bandwidth for improved video filtering and solves the dilemma on filter bandwidth design for multi-format video applications. The invention is applicable to video reconstruction filter applications requiring bandwidth adjustable filters.

Abstract: A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory.

Abstract: An integrated circuit device has multiple first circuit elements arranged in a first area. A signal distribution circuit that has multiple drive circuits is connected in the form of a tree structure and that distributes a common signal that is input to the starting point of said tree structure to each of the multiple first circuit elements through the same number of levels of drive circuits. At least some of the drive circuits of the tree structure are arranged one each in each of multiple second areas into which the first area is divided to include approximately the same number of the first circuit elements, and the common signal is supplied to the first circuit elements included in the second area where they are arranged.

Abstract: This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a scaled-down drive transistor employing varying drive codes compared with a standard. The thus determined drive code is combined with an offset to generate the drive code for the adjustable strength transistor.

Abstract: The timing stream is used to capture pipeline advances and to record stall cycles. Timing streams may be in standard or compressed formats. The stalls are traced concurrently with the PC trace. The data trace is used for holding the reasons for the external event. The timing stream also holds external event information, to assure cycle accuracy of the event being traced.

Abstract: A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing logic partitioning the status signals into classes according to one or more user-specified partition criteria.

Abstract: A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator input, during a sampling phase connecting the first side of a capacitor to an input and connecting a second side of the capacitor to a mid-voltage, following the sampling phase disconnecting the first side of the capacitor from the input and disconnecting the second side of the capacitor from the mid-voltage and autozeroing the comparator.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information is from caches on different cache levels associated with a common address. The processor also displays the information by way of a graphical user interface (GUI). The GUI displays a portion of the information using a mark-up technique different from that used to display remaining portions of the information.

Abstract: This invention is a programmable image pipe processing architecture that offers full software flexibility to implement latest and greatest algorithms at fully hardwired performance levels. This invention achieves hardwired image pipe processing performance but offers full flexibility and programmability of software achieving the best of both hardwired and software image pipes processing.

Abstract: Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically and the timing of channels is adjusted. In an embodiment, multiple sequences of parallel data elements are received on corresponding parallel data channels using a first common clock signal. Each sequence of parallel data elements is converted to a corresponding sequence of serial data elements. The serial data elements are transmitted on a corresponding serial channel using a serial clock as a common reference. A synchronization signal may be generated periodically with a time period of (the number of bits in each parallel data element x the time period of the serial clock), wherein ‘×’ represents multiplication operation. As the parallel data channels are synchronized in short intervals, synchronization is maintained.

Abstract: Pre filtering is commonly used in video encoding to remove undesirable noise from video sources. Without a pre filter, the noise degrades the performance of a video encoder by wasting a number of bits to represent the noise itself, and by introducing encoding artifacts such as blocking and ringing noise. However, excess use of pre filtering will degrade subjective visual quality. This invention employs an automatic pre filter control using a subjective noise detector capable of measuring noise that strongly correlates to subjective video quality.

Abstract: This invention samples and transmits the CEA-909 standard smart antenna analog pulse train waveforms using only a digital I/O pin for both mode A and mode B operation. This invention implements the smart antenna interface based on a single digital programmable counter. This counter is programmable so that it can tolerate or produce wide variation of symbol width.

Abstract: An extremely low overhead method calculates CPU load in the presence of both CPU idling and frequency scaling. The method measures time the CPU is idled while waiting for a wakeup. This invention uses a feature in current DSPs with the capability of delaying ISR processing on wake from IDLE. Using this mechanism it is possible to determine the time before IDLE, the time immediately following CPU wakeup, and then run the wakeup ISR. The delta time can be accumulated and compared to total time to determine true CPU load.

Abstract: A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an input signal to the tristate buffer and a gating stage having inputs for the input signal, a delayed input signal and an asynchronous tristate control signal and an output supplying the configuration signal to the tristate buffer. The gating stage sets the configuration signal to the high impedance mode only when the tristate control signal is set and the input signal and the delayed input signal have logic levels indicating that no signal transition of the input signal propagates within the delay stage. Depending upon signal polarity, the input signal and the delayed input signal are required to have the same digital state or opposite digital states.

Abstract: Rotation in the storage domain is a one-one function with the domain equal to the range. This permits an image to be rotated in place. Each image size implies at least one garland of closed chains of pixels. Each image includes a spanning set of these garlands. Rotation in place moves each pixel to the next location on its garland. On completion of a garland by return to the initial pixel, pixels on the next garland are moved. Image rotation is complete after all the garlands have been traversed.