Abstract: A hemodialysis and vascular access system which includes a catheter having an arteriovenous fistula utilizing an indwelling silastic venous end and an arterial end which is adapted to be anastomosed to an artery is described. The catheter includes a needle receiving s through which a needle is inserted to access fluid flow within the hemodialysis and vascular access system. The invention enables use of an “arterialized” indwelling venous catheter where blood flows from an artery through the hemodialysis and vascular access system and is returned to the venous system via an arrangement wherein the outflow opening is distinct and distant from the site where the catheter enters the vein. The site of blood return to the venous system is not directly fixed to the venous wall but is free floating within the venous system. This system provides a hemodialysis and venous access graft which has superior longevity and performance and is relatively easy to implant.

Abstract: A direct memory access (DMA) transmitter includes: (a) a data register; and (b) a transmitter state machine. Requested data at an address provided by a source is read from the random access memory then transferred for storage in the data register. The central processing unit also sends a control signal to the transmit state machine. The control signal indicates to the transmit state machine whether the read data is a most recent copy of the requested data in random access memory or whether the most recent copy of the requested data is still resident in the local cache memory. In response to the control signal, if the most recent data is in the local cache memory, the transmit state machine inhibits the data that was read from random access memory and now stored in data register from passing to the transmitter output. Transmit state machine then performs a second data transfer request at the same address, the second requested data being transferred from the local cache memory to the random access memory.

Abstract: A direct memory access (DMA) receiver adapted to receive data from a source, such data to be written into a random access memory is provided. The random access memory and DMA receiver being coupled are to a central processing unit by a bus. The central processing unit is coupled to a local cache memory. The source of such data provides an address for the data, such address being the location the random access memory where the data is to be stored. The DMA receiver includes an address register, a first data register and a duplicate data register. The duplicate register has an input coupled to an output of the first data register. A selector is provided having a pair of inputs, one being coupled to the output of the first data register and another one of the pair of inputs being coupled to an output of the duplicate data register. The selector couples one of the pair of inputs to an output thereof selectively in accordance with a select signal. A state machine is included in the DMA receiver.

Abstract: A data storage system wherein a host computer is in communication with a bank of disk drives through an interface. The interface includes: a memory; a plurality of directors for controlling data transfer between the host computer and the bank of disk drives as such data passes through the memory; and a plurality of busses in communication with the directors and the memory. Each one of the directors includes a central processing unit. The central processing unit includes: (A) a microprocessor; (B) a main memory; and (C) a microprocessor interface.

Abstract: A data storage system having a plurality of disk drives. Each one has a pair of ports. A pair of directors controls the flow of data to and from the disk drives. A first fibre channel port by-pass selector section is provided. The first fibre channel selector section includes: an input/output port coupled to a first one of the directors; and, a plurality of output/input ports connected between a first one of the ports of the plurality of disk drives through a first plurality of fibre channel links. The first fibre channel port by-pass selector section is adapted to couple the first one of the directors serially to one, or ones, of the first ports of the plurality of disk drives through a first fibre channel selectively in accordance with a control signal fed to the first fibre channel by-pass selector section. The first fibre channel includes one, or more, of the first plurality of fibre channel links.

Abstract: A system for efficiently representing or “mapping” data so that it can be rapidly communicated to a back-up storage system from a primary processor or a shared storage device while at the same time allowing a backup system to backup files rather than devices is described.

Abstract: A system having a memory with a plurality of contiguous processor memory regions and a plurality of processors. Each one of such processors is associated with a corresponding one of the processor memory regions. Each one of such processors provides a plurality of sets of successive processor addresses. The addresses in each one of such sets has a successive series of used addresses and a successive series of reserve addresses. The last used address in each one of the sets is separated from the first used address in the next successive set of addresses by a gap of addresses, G. A common address translator is fed by virtual addresses and maps the virtual addresses fed thereto to the memory addresses, such mapping being in accordance with the gap G to map each one of the sets of used processor addresses provided by each of the processors into the corresponding one of the contiguous processor memory regions.

Abstract: A radar detection process includes computing a derivative of an FFT output signal to detect an object within a specified detection zone. In one embodiment, a zero crossing in the second derivative of the FFT output signal indicates the presence of an object. The range of the object is determined as a function of the frequency at which the zero crossing occurs. Also described is a detection table containing indicators of the presence or absence of an object within a respective radar beam and processing cycle. At least two such indicators are combined in order to detect the presence of an object within the detection zone.

Abstract: A combined defense and navigational system on a naval vessel is disclosed. The disclosed system includes a track-while-scan pulse radar which is controlled to provide either navigational information or tracking information on selected targets. Additionally, the disclosed system includes a plurality of guided missiles, each of which may be vertically launched and directed toward intercept of a selected target either by commands from the track-while-scan radar or from an active guidance system in each such missile.

Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1−xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

Abstract: Electrical cabinet for storing a plurality of disk drives. The cabinet has an array of slots, each one of the slots being adapted to receive a corresponding one of a plurality of disk drives. Each one of the disk drive has a pair of ports. A printed circuit board mounted to a rear of the housing. The board having a plurality of plugs, each one of the plugs being positioned in registration with a corresponding one of the slots to make electrical connection to such corresponding one of the disk drives. The housing has a slot for receiving a pair of fibre channel port by-pass cards. The port by pass cards are electrically interconnected to the disk drives through the printed circuit board. Each one of such port-by pass cards is coupled to a corresponding one of a pair input/output ports through a corresponding one of a pair fibre channel transmission medium. Each one of the port by-pass cards is coupled to a corresponding one of the pair of ports of the disk drives.

Abstract: A fibre channel system having a plurality of disk drives. Each one of the disk drives has a pair of redundant ports. A pair of sources of data is provided. The system includes a pair of fibre channel port by-pass cards. Each one of the cards has an input/output port connected to a corresponding one of the sources of data. Each one of the port by-pass cards provides a fiber channel loop between the input/output port thereof and a corresponding one of the pair of ports of a one, or ones, of the disk drives selectively in accordance with a control signal fed to such port by-pass card by the one of the pair of sources coupled to the input/output port thereof. Each one of the port by-pass cards has a fail-over controller and a switch, such switch being coupled to the input/output port of such one of the port by-pass cards. Each one of the fail-over controllers produces a control signal from the source coupled thereto indicating a fault in the other one of the sources.

Abstract: A method and apparatus for connecting between a serial fibre channel link and a global memory provide a bidirectional high throughput path for enabling reliable communications and translation from the fibre channel format to the format required by the global memory. The apparatus includes, in series from the fibre channel link, a bidirectional physical interface, a bidirectional conversion circuitry for converting between an electrical protocol from the fibre channel and a high speed conventional protocol such as a PCI bus, a bidirectional lower machine controlled by a central processing unit and able to add block protection words to the passing data stream, and for separating the data stream into one of a plurality of pipes as directed by the CPU, an error detection and correction circuitry for adding yet additional error correcting data to the data stream as it written in the global memory and for detecting and correcting, if possible, any errors in data being retrieved from global memory.

Abstract: A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.

Abstract: A combined defense and navigational system on a naval Vessel is disclosed. The disclosed system includes a track-while-scan pulse radar which is controlled to provide either navigational information or tracking information on selected targets. Additionally, the disclosed system includes a plurality of guided missiles, each of which may be vertically launched and directed toward intercept of a selected target either by commands from the track-while-scan radar or from an active guidance system in each such missile.

Abstract: An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO). A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit.

Abstract: A data storage system having a plurality of disk drives. Each one has a pair of bidirectional ports. A pair of directors controls the flow of data to and from the disk drives. A first fibre channel port by-pass selector section is provided. The first fibre channel port by-pass selector section includes: an input/output port coupled to a first one of the directors; and, a plurality of output/input ports connected between a first one of the ports of the plurality of disk drives through a first plurality of fibre channel links. The first fibre channel port by-pass selector section is adapted to couple the first one of the directors serially to one, or ones, of the first ports of the plurality of disk drives through a first fibre channel selectively in accordance with a control signal fed to the first fibre channel by-pass selector section. The first fibre channel includes one, or more, of the first plurality of fibre channel links.

Abstract: A modular connector system for interconnecting printed circuit boards includes a first connector having an insulative housing supporting an array of blade-shaped contacts and a second connector having a complementary array of beam-shaped contacts. Preferably, each beam-shaped contact includes substantially independent coplanar beams which, in use, contact a common surface of a respective blade-shaped contact to provide multiple points of contact. The second connector includes a plurality of modules stacked in parallel. Each module includes a shield plate having an insulative receptacle attached at one end and a row of signal conductors, each having a beam-shaped contact at one end. Each insulative receptacle has a first side in which cavities are provided to receive the beam-shaped contacts of the signal conductor.

Abstract: A combined defense and navigational system on a naval vessel is disclosed. The disclosed system includes a track-while-scan pulse radar which is controlled to provide either navigational information or tracking information on selected targets. Additionally, the disclosed system includes a plurality of guided missiles, each of which may be vertically launched and directed toward intercept of a selected target either by commands from the track-while-scan radar or from an active guidance system in each such missile. The invention herein described was made in the course of or under a contract or subcontract thereunder, with the Department of Defense.

Abstract: A heat shield device suitable for use with a soldering device comprises a heat shield and means for moving the heat shield to and from the shielding position in which it shields a target area from a heat source, wherein the movement of the heat shield is mechanically linked to a movement of the heat source in relation to the target area. This device provides the advantage that the shielding of the heat source can be automatically synchronized with the movement of the heat source away from the target, the heat shield is secured with respect to the heat source by means of a resilient member which provides a biasing force to bias the heat shield away from the shielding position.