Abstract: A system and method is provided having a flash analog-to-digital converter (ADC) that includes an input signal buffer, a plurality of identical voltage comparators, and a reference generator. A clock signal defines the time instances at which the instantaneous input signal voltage is compared against a plurality of reference voltages generated by the reference generator. The individual comparator consists of a an integrating amplifier stage followed by an analog latching stage and a digital latch. The integrating amplifier input is allowed to track the input signal continuously. The amplifier output voltage is forced to a voltage close to zero before each conversion cycle is initiated by the ADC clock. At the beginning of the conversion cycle, the amplifier output is released and its voltage will follow an excursion related to the integral of the input of the amplifier. At a predefined time moment later, the analog latch is activated.

Abstract: A system and method for correcting comparator offsets which occur during operating conditions such that static and dynamic offsets are compensated is provided. The comparator may be calibrated for normal operating conditions. The calibration may be accomplished by providing adjustability of the comparators' threshold value and providing a feedback loop for adjusting the threshold value. In one preferred embodiment, the comparator may be utilized within a flash ADC, and in a more preferred embodiment, the comparator may be utilized within a flash ADC of a read/write channel circuit.

Abstract: A compact disk (CD) and digital video disk (DVD) error correction system is disclosed which generates a CRC validation syndrome on-the-fly while correcting the CD/DVD product code, thereby reducing the overall access latency as compared to the prior art. For the DVD product code, which comprises multiple data sectors with separate CRC symbols appended to each data sector, a buffer used for C1 and C2 encoding/decoding in CD mode is used to store partial data and error CRC syndromes for each data sector. During the vertical (P) and horizontal (Q) passes over the DVD product code, data and error CRC syndrome registers are loaded with the appropriate partial CRC syndromes depending on the current data symbol being processed by a P/Q decoder. After processing each data sector, the data and error CRC syndromes for each data sector are combined and compared to a constant to determine whether the corrections to the data sector are valid and complete.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, computes a DC offset in the sample values in real time, and subtracts the DC offset from the read signal. This attenuates the deleterious affect a DC offset has on the detection algorithm used to detect the recorded data, such as the Viterbi detection algorithm.

Abstract: Methods and apparatus for the processing of digital signals having high speed and low power dissipation. The apparatus uses Residue Number Systems (RNSs) to represent the signals and/or parameters, with each digit within an RNS system being encoded in a "one-hot" encoding scheme wherein each possible value of a digit has an associated single line, one and only one of which will be high at any one time. The combination of an RNS system with the one-hot scheme results in low signal activity and low loading of signal lines which in turn result in low power. Methods and apparatus for addition, subtraction, multiplication and other operations, and conversion from and to natural numbers. The speed advantage offered by other RNS-based architectures is retained.

Abstract: A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons.

Abstract: An improved write precompensation circuit for a read/write channel circuit and system is provided. Multiple data input signals are provided, each being clocked by a different clock. The data input signals are then multiplexed. Two, three or more data clock delays may be utilized to provide two, three or more data delays to achieve the write precompensation. Only one edge of a signal need pass through a multiplexer before the multiplexer may change state. The amount of delay may be user programmable.

Abstract: An optical disc storage system comprises a sliding mode controller for actuating an optical read head assembly over an optical disc during focus capture, focus tracking, track seeking and centerline tracking. The sliding mode controller is a non-linear control system which operates by switching between positive and negative feedback in order to force certain phase states (such as the read head's position error and velocity) to follow a predetermined phase state trajectory. Sliding mode control provides improved compensation to parametric variations, external load disturbances and other transients such as, for example, the focus capture transient. Furthermore, the sliding mode positive and negative feedback gains need only be within a predetermined range, thereby allowing gain values of 2.sup.n which significantly reduces the complexity and cost of the gain multipliers.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. A Channel Quality circuit accumulates various signals generated by the read channel, such as sample errors, gain errors, timing errors, etc., for use in calibrating the read channel components and estimating the bit error rate.

Abstract: An efficient error correction processor is disclosed for correcting a multi-dimensional code comprising a first set of codewords that intersect with a second set of codewords. The error correction is carried out by performing iterative passes over the first and second set of codewords. The individual codewords are corrected using error syndromes which are computed as a function of the codeword data. In the preferred embodiment, the individual codewords are encoded according to a Reed-Solomon code and the error syndromes are computed as the modulo division of the codeword polynomial by the factors of a generator polynomial. To increase the throughput of the error correction processor, a syndrome buffer is employed to facilitate generating the error syndromes for both the first and second set codewords concurrently. In this manner, after a pass over the first set of codewords, the error syndromes for the second set codewords are available for immediate processing.

Abstract: A sampled amplitude read channel for disk storage systems is disclosed which asynchronously sub-samples an analog read signal significantly below the Nyquist rate (the baud rate) in order to increase the effective data rate without increasing the frequency of the sampling device. Interpolated timing recovery up-samples the asynchronous samples to generate sample values synchronized to the baud rate, and a Viterbi sequence detector detects the recorded digital data from the synchronous sample values. To compensate for the time-varying characteristics of the recording device, a discrete-time equalizer adaptively equalizes the asynchronous sample values using a least mean square (LMS) adaptive algorithm,W.sub.k+1 =W.sub.k -.mu..multidot.e.sub.k .multidot.X.sub.k,where W.sub.k is a vector of FIR filter coefficients, .mu. is a programmable gain, e.sub.k is a sample error between the FIR filter's actual output and a desired output, and X.sub.k is a vector of samples values from the FIR filter input.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a partial response of the form (1-D)(1+D).sup.n where n>1, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector.

Abstract: A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by detecting an estimated binary sequence from a sequence of discrete-time sample values generated by sampling pulses in an analog read signal from a read head positioned over the disk storage medium. The read channel comprises a variable gain amplifier for adjusting the magnitude of the analog read signal before sampling, and a discrete-time gain control loop for generating a gain control signal applied to the VGA in response to the discrete-time sample values. The discrete-time sample values may, or may not be, synchronized to a baud rate of the recorded data. For example, when reading the user data the discrete-time sample values are synchronous, and when reading a servo address mark (SAM) the sample values are asynchronous. As such, the discrete-time gain control loop of the present invention is programmable to operate in a synchronous or asynchronous mode.

Abstract: In an optical disk storage device, a differential phase detector is disclosed for generating a position error signal independent of the frequency content of the recorded data. A pair if diagonal signals S1 and S2 are generated by adding a pair of respective quadrants of a four-quadrant photodetector, where the phase offset between the diagonal signals represents the position error of the pit image as it passes over the photodetector. The position error is determined in the present invention by computing the difference between a positive and negative correlation of the diagonal signals S1 and S2, otherwise referred to as a dual arm correlation (DAC) ##EQU1## where .DELTA. is the correlation offset and L is the correlation length. In the preferred embodiment, the correlation offset .DELTA. is adaptively adjusted to maximize the correlation between S1 and S2. In this manner, the position error estimate is substantially insensitive to the frequency content of the recorded data.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems that employs a remod/demod sequence detector guided by an error syndrome of an error detection code (EDC). The remod/demod sequence detector comprises: a conventional trellis type maximum likelihood sequence detector, such as a Viterbi detector, for detecting a preliminary binary sequence from the channel sample values; a syndrome generator for generating an error syndrome in response to the preliminary binary sequence; a remodulator for remodulating the detected binary sequence into a sequence of estimated ideal sample values; a sample error generator for subtracting the channel samples from the estimated samples to generate a sample error sequence; an error pattern detector for detecting potential error events in the sample error sequence; and an error corrector for correcting the preliminary binary sequence when the error syndrome indicates that an error occurred.

Abstract: An error detection and correction system is disclosed for efficiently processing a product code typically employed in an optical storage device. In particular, the present invention decreases the processing time associated with iteratively processing the rows and columns of the product code by processing only those code words that were "flagged" during a previous iteration. If, for example, while processing the column code words a byte in a column code word is corrected, then the corresponding intersecting row code word is flagged for processing during the "row pass." Only the row code words that have been flagged are processed during the "row pass", which significantly reduces buffer access latency and increases the overall throughput of the storage system. To assist in error detection and correction, an array of erasure pointers is employed where each erasure pointer corresponds to a byte in a code word.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.

Abstract: A trellis sequence detector is disclosed for detecting a quadrature servo signal in optical disk storage devices. The quadrature servo signal is generated in discrete time and comprises two sinusoidal signals phase offset by 90 degrees. The sampling frequency of the quadrature signal is controlled relative to the track crossing velocity so as to produce a fixed number of samples per period of the sinusoid (i.e., per track crossing). In the embodiment disclosed herein, the sampling of the sinusoidal signals is controlled such that there are eight samples per track crossing. The eight samples are associated with a state transition diagram and corresponding trellis diagram which define the operation of a trellis sequence detector. The trellis sequence detector processes the actual samples of the quadrature signal to determine an estimated quadrature sequence closest to the actual samples of the quadrature signal.

Abstract: A descrambler for a Digital Versatile Disk (DVD) is provided within a DVD controller to allow for real-time descrambling of DVD data from the DVD buffer. The built-in descrambler also allows the controller to interface with a Host Adapter (e.g., ATAPI Host) or MPEG II decoder. The descrambling circuit reads four bits of an identifier portion of each sector. These four bits are used to access a look up table LUT in the descrambler for retrieving a 15 bit seed. The fifteen bit seed is used to generate a descrambling patter, which, when XORed with scrambled data, will descramble data on a byte-by-byte basis. The descrambling pattern is generated on a flash basis, by performing eight shift operations and XOR operations simultaneously, allowing for descrambling one byte per clock cycle.

Abstract: In an optical disk storage device wherein user data is demodulated from a light beam reflecting off data pits in tracks of an optical disk storage medium, a quadrature seek signal is generated indicative of the light beam crossing tracks of the optical disk during a seek operation. The quadrature seek signal is generated from a discrete-time tracking error signal (TES) and a discrete-time RF baseband signal. The discrete-time TES is generated according to the mode of operation, compact disk (CD) or digital video disk (DVD). In CD mode the TES is generated as the difference between E and F tracking photodiodes, and in DVD mode the TES is generated using a discrete-time differential phase detector (DPD). To generate the discrete-time RF baseband signal, the RF data signal (generated as the sum A+B+C+D of a four quadrant photodiode) is sampled at the channel rate and the RF data samples passed through a discrete-time envelope detector.