Abstract: In a data arithmetic logic unit (54), power consumption is reduced by eliminating unnecessary write backs to the destination register (82) following a MAC (multiply/accumulate) operation. A series of instructions provided to the data ALU (arithmetic/logic) (54) are monitored by a control circuit (89). When two or more consecutive instructions having identical destinations for a result are detected, the result is written to a pipeline register (78) instead of to the destination register (82) named in the consecutive instructions. Thus, only a short, lightly loaded bus to the pipeline register (78) is driven, instead of the longer heavily loaded bus to the destination register (82).

Abstract: A data processing system (10) and associated method (150) of operation selectively compand data on a slot-by-slot basis. The data processing system (10) includes a processor (12), processor bus (14), memory (16), output serial interface (18), and input serial interface (70). The output serial interface (18) includes an output data buffer (20), compression module (22), output shift register (24), and output controller (26). In operation, the output serial interface (18) receives output data (28) and selectively compresses the data on a slot-by-slot basis. The shift register (24) then places the transmit data (32) on the serial link (25). An input serial interface (128) selectively expands data received on the serial link (25) on a slot-by-slot basis to produce input data (82). The associated method (150) includes method steps for companding data on a slot-by-slot basis. An ISDN interface and digital telephone (200) employ the teachings of the present invention.

Abstract: Logic test vectors, used for testing logic circuitry on a logic tester, are converted to test patterns having a format that is used by a memory tester. This allows an integrated circuit having both logic circuitry and a memory array to be tested on a memory tester. A software tool, or computer program, is used to convert the logic test vectors to test patterns, and also generates the memory test code for applying the test patterns to, for example, a logic intensive integrated circuit memory. The software tool is encoded using a high-level programming language and is executed on a computer system (60). The program allows the logic intensive integrated circuit memory to be tested on a memory tester, as compared to testing the integrated circuit memory on a logic tester, significantly reducing testing costs associated with manufacturing.

Abstract: To execute a three-dimensional DMA transfer, a transfer counter register (76), which is partitioned into three sections, is loaded with initial counter values. Each section of the counter register (76) is independently controlled by a counter (72, 73, 74). Data is transferred from consecutive generated addresses for a first predetermined number of times as determined by the value in the first section of the counter register (76). An offset value is then added to a last generated address. The process is repeated for a second predetermined number of times. Then another offset value is added to the generated address. This entire process is repeated for a given number of times as determined by the third section of the register (76). The initial counter values are reloaded into counter register (76) from a backup register (77), insuring that a DMA controller (80) is ready if a new transfer request requires the same counter values as the previous transfer.

Abstract: A circuit having a combined level conversion and logic function (37, 90, 101, 102, and 103) receives a differential CMOS level input signal, and an input signal having a relatively small logic swing, performs a logic operation, and provides a single-ended CMOS output signal. The circuit (37) includes a CMOS switching portion (71) and a small signal switching portion (75) connected to provide a CMOS output signal that is the result of a logical operation of the input signals. The circuits (37, 90, 101, 102, and 103), eliminate the need for a separate level converter, reducing at least a gate delay, and insuring faster generation of the output signal. Also, the use of the circuit (37) having a combined level conversion and logic function allows the cache TAG (20) to provide read data at the same time that a match signal is generated.

Abstract: A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

Abstract: An output buffer circuit (20) has an output impedance that is adjustable. An external resistor (32) having a resistance that is a multiple of the desired output impedance is coupled to the output buffer circuit (20). A voltage across the resistor (32) is converted to a digital code using an analog-to-digital (A/D) converter (22). A digital code from the A/D converter (24) is used to adjust a resistance of a binary weighed transistor array (45) to match the resistance of the external resistor (32). A plurality of binary weighted output transistors (153, 154, 155) are selected in response to the digital code to adjust the output impedance to match the characteristic impedance of a load driven by the output buffer circuit (20). The output impedance is easily adjustable by changing the resistance of external resistor (32), allowing the output buffer circuit to drive various load impedances.

Abstract: A data ALU (arithmetic logic unit) (54) in a data processing system (20) performs both 24-bit arithmetic, and 16-bit exact arithmetic (including shifting and logical operations) using the same hardware. For a multiply/accumulate operation in 16-bit exact mode, shifting operations are used to align the operands so that 16-bit exact mode is transparent to a user. An entire instruction set can be executed in 24-bit mode or 16-bit exact mode. The same instructions and hardware are used in both modes. A transition between modes is performed by changing a status bit (97) in a status register (95).

Abstract: A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A comparator/latch (50) compares a new address to a previous address and generates an address match signal that is used to select match sense amplifiers (52) and deselect regular sense amplifiers (54). Relatively fast address comparison and address match signal generation is accomplished using a comparator/latch (50) for each column address signal, and emitter summing each match signal to provide the address match signal. The use of emitter summing reduces a number of gate delays, thus allowing the address match signal to be generated before the regular sense amplifiers (54) can be selected, and allowing the read global data lines to be shared without increasing the access time of the integrated circuit memory (30).

Abstract: A compensation circuit (64) for ensuring that a first conductor (60) of a plurality of parallel conductors (60, 61, 62) in a bus (50) remains at a logic high voltage when a second conductor (61) adjacent to the first conductor (60) transitions from a logic high voltage to a logic low voltage. The compensation circuit (64) senses when the voltage on the second conductor (61) is reduced from a logic high voltage to a logic low voltage, and causes the first conductor (60) to be coupled to a power supply voltage terminal to prevent a logic high voltage on the first conductor (60) from being reduced toward a logic low voltage due to a capacitive coupling between the first conductor (60) and the second conductor (61).

Abstract: An integrated circuit memory (114) has a power supply independent address buffer (50) that comprises an inverter (60), a bipolar transistor (67), and a P-channel transistor (68). The inverter (60) has an output terminal coupled to a base of the bipolar transistor (67). The P-channel transistor (63) is for injecting a current at the output terminal of the inverter in response to a reference voltage. The reference voltage varies proportionally to variations of a power supply voltage in order to compensate for gate-to-source voltage changes of a P-channel transistor (61) of the inverter (60) that occurs as a result of a changing power supply voltage. For address buffer (50), a range of address transition times as a function of power supply voltage is decreased, thus improving an address set-up and hold time of the integrated circuit memory (114).

Abstract: An integrated circuit memory (20) has a write pulse generator (38) for generating a self-timed write pulse independent of system clock frequency and system clock duty cycle. The write pulse generator (38) includes a delay element (56) and a delay element (68). The write pulse is triggered on a rising edge of the clock signal and has a duration that is determined by a delay time provided by the delay element (68). The delay elements (56, 68) provide single-sided delays and compensate for process, power supply, temperature variations of the integrated circuit memory (20).

Abstract: An N+1 frequency divider counter (20) has a binary counter (22), ones detect circuitry (26), control logic (24), and an output flip-flop (28). The binary counter (22) counts from an initial value to a final value for each half of an output clock signal. If N+1 is an even number, one full cycle is added to each half cycle of the output clock signal. If N+1 is an odd number, one-half of a cycle is added to each half phase of the output clock signal. At the final count value, the control logic (24) causes the output clock signal to transition on either the rising edge or the falling edge of an input clock signal. The N+1 counter (20) has a fifty percent duty cycle for all count values of N, and does not require additional circuitry to accommodate when N equals zero.

Abstract: A current mode transmitter (21) receives an input signal and converts the input signal to a current having at least two values. The current is transmitted across a transmission line (27) to a current mode receiver (30). The current mode receiver (30) has a low impedance input node (102) coupled to the transmission line (27) for receiving the current. Complementary voltage-follower transistors (35, 36) in the receiver (30) are connected to the transmission line (27). A current mirror (31, 42) is coupled to each of the voltage-follower transistors (35, 36) to convert the current to a CMOS signal. The reduced signal swing of the transmitted signal reduces RFI emissions as compared to a signal having a larger signal swing.

Abstract: An integrated circuit memory (30) having redundancy shares read, global data lines shared between a regular memory array (35) and a plurality of redundant columns (41). Redundant data and regular data are multiplexed onto the read global data lines by emitter summing bipolar transistors of regular sense amplifiers (46) with a redundant multiplexer (83). When a redundant column is used to replace a defective regular column, a match circuit (88) generates a match signal for selecting a redundant multiplexer circuit (84, 85, or 86) and for deselecting a corresponding regular sense amplifier (46). The match circuit (88) includes emitter summing circuits (230, 240) to rapidly generate the match signal.

Abstract: A cache TAG comparator (20) has a combined data multiplexer and compare circuit (30) for multiplexing redundant columns (26) with normal columns of memory cells and for comparing input data with a TAG address stored in a TAG array (21) for determining if data required by a data processing system is located in a corresponding cache memory. A BICMOS match logic circuit (40) receives a compare signal from each data multiplexer and compare circuit, and provides a logic high match signal indicating a cache hit in response to a logic state of the input data and the TAG address being identical. The comparison is performed in ECL, allowing high speed operation. Also, the match signal is generated prior to a critical read path, insuring faster generation of the match signal.

Abstract: A BICMOS output buffer circuit (20) has a voltage converter (21), a reference voltage circuit (28), a driver circuit (24), and a clamping circuit (40). The reference voltage circuit (28) receives a regulated voltage and provides a reference voltage having a low voltage level and a high voltage level. The low voltage level and the high voltage level control the logic high voltage of an output data signal. During a transition from a logic low voltage to a logic high voltage of the output data signal, the output data signal is allowed to overshoot the low voltage level. After the transition is complete, the output data signal settles at the high voltage level. This limits the amount of overshoot of the output data signal. The clamping circuit (40) dampens the oscillations of the output signal.

Abstract: A nonvolatile SRAM cell (20) includes a six-transistor SRAM cell portion (22) and a three-transistor nonvolatile memory portion (30). The nonvolatile memory portion (30) is connected to one storage node (101) of the SRAM cell portion (22). The nonvolatile SRAM cell (20) is three-dimensionally integrated in four layers of polysilicon. The nonvolatile memory portion (30) includes a thin film memory cell (32) having an oxide-nitride-oxide structure (41), and is programmable with a relatively low programming voltage. The three-dimensional integration of the nonvolatile SRAM cell (20) and relatively low programming voltage results in lower power consumption and smaller cell size.

Abstract: A nonvolatile SRAM cell (20) includes a six-transistor SRAM cell portion (22) and a three-transistor nonvolatile memory portion (30). The nonvolatile memory portion (30) is connected to one storage node (101) of the SRAM cell portion (22). The nonvolatile SRAM cell (20) is three-dimensionally integrated in four layers of polysilicon. The nonvolatile memory portion (30) includes a thin film memory cell (32) having an oxide-nitride-oxide structure (41), and is programmable with a relatively low programming voltage. The three-dimensional integration of the nonvolatile SRAM cell (20) and relatively low programming voltage results in lower power consumption and smaller cell size.

Abstract: An ECL multiplexing circuit (20) includes two differential pairs (21 and 22) for receiving first and second ECL level input signals, emitter-follower output transistors (27 and 28), and a differential pair (31 and 32) for receiving differential clock signals. The differential clock signals control which of the two differential pairs (21 and 22) is coupled to the emitter-follower output transistors (27 and 28). The ECL level input signals that control a logic state of the output signals is determined by the logic state of the clock signals. The ECL multiplexing circuit (20) receives non-overlapping clock signals and is used in a quadrature frequency divide-by-two circuit (40) to divide a frequency of an input clock signal by two.