Abstract: A memory (20) has a read cycle and a write cycle. During the read cycle, differential data signals, corresponding to data provided by a selected memory cell, are superimposed on a first common mode voltage and provided to data output buffers (70-73). During the write cycle, differential data signals on read global data lines (61-62) are equalized at a second common mode voltage and data output buffers (70-73) are disabled. Output enable circuit (74) provides an output enable signal halfway between the first and second common mode voltages. Data output buffers (70-73) are enabled at the beginning of the read cycle when the differential data signals cross the output enable signal as they transition from the second common mode voltage to the first common mode voltage. Enabling data output buffers (70-73) in this way greatly relaxes output enable timing constraints.

Abstract: An ECL logic gate (70) includes a voltage protection clamp (60) for protecting a first bipolar transistor (58) from being too heavily reverse biased when an input signal A.sub.IN is pulled to V.sub.SS. The ECL logic gate (70) includes an emitter-follower input stage and a differential amplifier stage. A voltage protection clamp (60) includes a second transistor (52) and a resistor (53) and acts to divide the amount of reverse bias on the first bipolar transistor (58) between a third transistor (51) and the first transistor (58), thereby bringing the reverse bias voltage on the first transistor (58) within acceptable levels to prevent degradation of the first transistor (58).

Abstract: A BICMOS NAND gate (40) has a CMOS NAND gate (41), a bipolar pull-up transistor (47), a bipolar pull-down transistor (48), series connected N-channel transistors (43-45) coupled between the base and collector of pull-down transistor (48), N-channel transistors (42, 46, 49, and 50), and a V.sub.BG generated reference voltage (51). N-channel transistor (46) receives a variable bias voltage provided by transistors 49, 50, and V.sub.BG generated reference voltage (51). At high power supply voltages, N-channel transistor (46) prevents pull-down transistor (48) from becoming saturated when BICMOS NAND gate (40) is operating at high frequency, when an input becomes skewed, or a glitch develops, yet allows for satisfactory operation BICMOS NAND gate (40) at low power supply voltages.

Abstract: A low power level converter (20), for converting from one logic level to another, includes six transistors (21 through 26). Two transistors (23 and 25) are connected to form a current mirror. A power supply voltage is provided to both sides of the current mirror through a third and a fourth transistor (22 and 26). The third and fourth transistors receive complementary signals V.sub.I and V.sub.I. A fifth transistor (21) is connected between the third transistor and the power supply, and a sixth transistor (24) is connected across the current mirror. An output signal, provided at the mirror side of the current mirror, is fed back into the converter at the control electrodes of the fifth and sixth transistors and utilized to prevent a constant undesirable DC current from flowing between the power supply voltage terminals, thereby reducing the power consumption of the converter. One embodiment uses P-channel and N-channel transistors.