Abstract: A method and system for reserving dynamically and in priority for each link of the network the exact amount of bandwidth necessary for the transmission of the network control traffic. An evaluation of the expected control traffic on each link of the network is performed in order to allocate a sufficient but minimum fraction of the link bandwidth and for allocating the maximum available bandwidth for the user traffic.

Abstract: Programs stored in memory devices associated with microcontrollers controlling a display to a user are constructed in a language which uses layered statements, each of which can have a description portion, an action portion, and a unique connecting character.

Abstract: A display generating system, particularly a computer or mobile client system, in which a system message (by which is meant an unsolicited prompt from a computer system to a user) is displayed to a user in a manner particularly contemplated as attracting the attention of the user. Accommodating such a system message in the small screen area available in a mobile client computer is a particular problem, addressed and solved as here described.

Abstract: This invention relates to a video graphic control method and controller for sending to a display device graphic data from a processing device, and the object thereof is to provide a video graphic controller that increases the bandwidth available to a graphic engine or CPU without increasing power consumption or manufacturing costs, even when used with a conventional frame memory. A video graphic controller for controlling video data by storing the video data from a CPU 4 in a frame memory 18 and causing the frame memory 18 to output the data to a display device 30 uses a video data comparison means 20 to compare a piece of video data stored in the N-th address of the frame memory 18 to another piece of video data stored in the N-1-th address in order to determine whether the two pieces of data match, and if the two pieces of data match, outputs to the display device 30 the piece of video data stored in the N-1-th address instead of the piece of video data stored in the N-th address.

Abstract: An information processing system that can reduce the operating frequency of a CPU, or halt the operation of the CPU, at an adequate timing, even when the system is engaged in exchanging data with another independent apparatus (e.g., another PC) via a communication port (a serial port or a parallel port), or when a communication application is being executed.

Abstract: A system and method for searching a large volume of data stored in a disk in, for example, document file format at a high speed while allowing desired ambiguity. The present invention provides a character string search scheme which enables a user to optionally designate the degree of ambiguity for a character string to be searched. The present invention also provides an index structure for implementing a character string search scheme which enables a user of the search scheme to optionally designate the degree of ambiguity for a character string to be searched. The present invention also provides a character string search scheme which enables the scheme to perform searches in a manner close to human feeling by ambiguity search. Details of the manner in which such enablements are implemented are found in the detailed specification.

Abstract: A method and an apparatus for reducing the jitter and end-to-end delay on lines of a packet switching network conveying voice or video digitalized data for one or more connections between a local source and a remote source at a constant bit rate.The method and apparatus of the invention are for use in a voice or video processor of a voice or video processing server of a network node; the method and the apparatus provide a way of controlling the remote traffic rate from the remote source before accessing the processor without using an external clocking such as the network clock.The solution proposed by the invention consists in buffering the remote and local traffics to adapt the remote traffic rate to the local traffic rate, which is supposed having a limited jitter, while sequencing of the access of the buffered data to the processor.

Abstract: A multimedia display system includes a central processing unit, a storage device associated with the central processing unit, a standard interface bus to which the central processing unit and the storage device are connected, a graphics processor connected to the bus for generating graphics data in response to commands from the central processor, a digitizer for converting an analog video signal to digital form and for producing synchronization signals, a video processor for processing the digitized video data to produce pixel representations of the digitized video signal, a shared frame buffer for storing the graphics data generated by the graphics processor and the pixel representations of the video signal, a device for converting the stored digital data to a data stream appropriate for driving a video monitor, and a video monitor for displaying the graphics data and the video information, wherein the video processor generates a programmable variable phase vertical synchronization signal for synchronizing v

Abstract: A memory refreshing system that can dynamically execute a self-refresh operation, even though the computer system is in a normal operational mode and can thus save the power consumption, and includes a memory refreshing system, for a memory system including a plurality of memory banks, which comprises a memory refreshing device, provided in each of the memory banks, for performing a refresh operation within a corresponding memory bank by, e.g.

Abstract: A computer, and particularly a mobile client computer system, in which flexibility in use of the system is enhanced by a capability of receiving and dynamically recognizing a variety of what are here called docking options. Docking options are peripheral devices, such as radio transceivers, which can be selectively connected to and used with a mobile client system. A docked option is identified by an exchange of signals between the system and the option, accomplished through a plurality of input/output ports which together define an interface to the option.

Abstract: A coordinate input system to which control data (a displacement value), concerning the location and the posture of a displayed graphic object, can be input with a conventional coordinate pointing device, such as a mouse, and a method therefor. Coordinate values of three sequential input points P.sub.n, P.sub.n+1 and P.sub.n+2, which are entered with a coordinate pointing device, such as a mouse, are employed to calculate the central angle .angle.P.sub.n O.sub.n P.sub.n+2 relative to the arc P.sub.n P.sub.n+1 P.sub.n+2 of the circle O.sub.n circumscribed about these three points. Then, the angle .angle.P.sub.n O.sub.n P.sub.n+2 is employed to acquire the central angle .angle..theta..sub.n for the arc P.sub.n P.sub.n+1. A logic circuit or an upper-level program that waits for the input of the dial rotation value as control data employs the central angle .angle..theta..sub.n, which is acquired by inputting the coordinate values of the two sequential points P.sub.n and P.sub.

Abstract: The method and apparatus of the present invention solve the problem of scheduling the transmission of cells in packet switched networks having network connections requiring a minimum bandwidth at connection establishment. The method and the apparatus further support any mixed traffic flow including connections requiring a minimum bandwidth, a fixed reserved bandwidth or no bandwidth at connection establishment. Scheduling is controlled by a dual scheduling mechanism having a first scheduler, triggered by absolute time, for scheduling the minimum service connections up to a rate corresponding to their reserved minimum bandwidth, a second scheduler and a queue of minimum service connection identifiers for communication between the two scheduling schemes.

Abstract: A computer system such as a mobile client system in which provision is made for management of flash memory. Flash memory management is done using variable block length and supports data compression. Blocks are allocated contiguously in each erase unit and each block starts with a header that contains the length of the block. Blocks are tracked using a single-level virtual address map which resides in random access memory (RAM). The mobile computer system may also include a housing, processor, random access memory, display and an input digitizer such as a touchscreen.

Abstract: Provided is a PC card and peripheral device having a non-volatile memory device that can perform erasing and re-writing at a relatively high operational voltage, and an internal circuit that is driven at a relatively low voltage, and is accomplished by a typical PC card that comprises: (a) an EEPROM serving as a non-volatile memory device; (b) a built-in battery having a low voltage output that supports the reading of the EEPROM but does not support erasing and re-writing; (c) a power line for conveying from a host computer system the high voltage required for erasing and re-writing the EEPROM; (d) an MPU that can be driven by a voltage supplied by the built-in battery; (e) an interface circuit that can be driven at a voltage supplied by the built-in battery; and (f) a switching circuit for selecting either the built-in battery or the power line as the power supply for the EEPROM.

Abstract: The present invention is a clock generator circuit using semiconductor integrated circuits and which has an input logic circuit to which an external clock signal is supplied; a delaying element chain in which a plurality of delay elements connected to the input logic circuit are serially connected together; a plurality of delay element selectors connected to each of the plurality of delay elements, respectively; a loop closing circuit connected to the delay element connected to a specific delay element selector which to a state indicating a selected status and to the input logic circuit, for forming a closed loop between the delay element chain and the input logic circuit; and an external output connected to the input logic circuit.

Abstract: A data transmission method for transmitting data from a first processing unit having a relatively large memory capacity to a second processing unit having a relatively small memory capacity. The method has steps of (a) retrieving data stored in a first memory device, (b) storing in a temporary file only a record, from the retrieved data, relating to a predetermined time period including a current date; (c) determining whether or not the size of the temporary file is within the capacity of a second, smaller capacity, memory device; and (d) transferring the temporary file to the second processing unit in response to an affirmative result of the step (c), or not transferring the temporary file to the second processing unit in response to a negative result of the step (c).

Abstract: A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.

Abstract: A desktop computer system having the capability to suspend and resume the state of the computer system. The suspended system state is saved to the system hard file such that system power may be removed, effectively allowing a system suspend requiring no power from the power supply.

Abstract: A communication system and method of communicating including a slave function connected to a master function by a single address bus, a write data bus and a read data bus so as to allow for overlapping multiple cycle read and write operations between the master function and the slave function. Preferably the communication system includes a plurality of slave functions connected to a master function by the single address bus, the write data bus and the read data bus. A plurality of master functions may be connected to the slave functions through a bus arbiter connected to the plurality of master functions by an address bus, a write data bus and a read data bus for each master function. The bus arbiter receives requests for communication operations from the plurality of master functions and selectively transmits the communication operations to the slave functions.