Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus.

Abstract: A computer system comprising a central processing unit (CPU) configured to accept coordinate type data from a touchpad or the like. The CPU has an operating system executing thereon with special support for interfacing to the touchpad. The operating system has the following capabilities: (1) mapping out geometric regions of the touchpad and assign the regions to specific region identifiers responsive to application programs and (2) determining the region identifier of a touched region and passing that region identifier to the application program. Support is also provided for changing the units of the commands used to define the regions.

Abstract: A video display, which may be a television receiver with associated set top device, an intelligent television receiver, or a personal computer system enabled for television display, has associated therewith a remote control which controls modification of the visual images displayed. By use of the remote control, a human observer may cause a processor controlling the video display to execute a control program formulated in a particularly concise language and controlling the display of menus and the like. Menus are displayed as overlays onto a live motion video image. A display controller and video reception circuitry cooperating for displaying full motion video visual images occupying substantially the entirety of a viewable screen area and a menu display occupying a minor portion of the screen area and overlying the full motion video visual images.

Abstract: A video display, which may be a television receiver with associated set top device, an intelligent television receiver, or a personal computer system enabled for television display, has associated therewith a remote control which controls modification of the visual images displayed. By use of the remote control, a human observer may cause a processor controlling the video display to execute a control program formulated in a particularly concise language and controlling the display of menus and the like.

Abstract: A video display, which may be a television receiver with associated set top device, an intelligent television receiver, or a personal computer system enabled for television display, has associated therewith a remote control which controls modification of the visual images displayed. By use of the remote control, a human observer may cause a processor controlling the video display to execute a control program formulated in a particularly concise language and controlling the display of menus and the like. Menus are displayed as overlays onto a live motion video image. A display controller and video reception circuitry cooperating for displaying full motion video visual images occupying a minor portion of a viewable screen area and a menu display occupying a major portion of the screen area.

Abstract: Principal data (e.g. frequently accessed data such as video BIOS program information and a principal font set) and secondary data (e.g. secondary font sets) are permanently stored in a slow memory device (e.g. EPROM). To improve performance, the principal data but not the secondary data is copied initially to a faster access memory device (shadow RAM). Translating logic associated with the latter device is initially configured to intercept memory requests, having addresses in a range preassigned to the EPROM, and redirect them to shadow RAM. However, in order to allow for access to the secondary data, the redirection function of the translating logic can be disabled and re-enabled, under control of programs running in an associated computer, so that requests in the preassigned address range are routed directly to the EPROM. When the translating logic is disabled, all of the EPROM becomes accessible including locations containing the principal data and locations containing the secondary data.

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The storage controller in accordance with this invention has internal volatile memory for transitory storage of data being communicated to coupled volatile memory. It further has control drivers interposed between the internal volatile memory and external volatile memory for controlling communication of data to the external volatile memory, with an enable driver and an enable receiver enchained between the control drivers and a source of signals controlling data communication.

Abstract: A method of saving and restoring the state of a CPU operating code in protected mode on a computer system. The save method makes use of BIOS operating in shadow RAM located in a region where linear addresses equal physical addresses while saving the state of the CPU. The registers that cannot be directly saved to memory are determined by searching the system memory for data structures that correspond to the particular register. The restore method uses dummy page tables that point to the shadowed BIOS to allow the CPU to reenter protected mode without generating a protection fault.

Abstract: A data handling arrangement for a computer system, with particular application to multimedia systems, allows device adapters (control units) attached to the system to autonomously (without interrupting the system processor) control processing of a data stream of arbitrary length through memory buffers which are smaller than the stream. In this (stream processing) operation, data constituting the data stream flows through devices controlled by the adapter in succession, and is held in shared memory buffers as it passes between devices. The adapters are prepared for the stream processing operation by a system processor, indicate their preparation status to the processor, receive an initiating signal from the processor, and then proceed to direct the operation to completion without further assistance from the processor. In the operation, the adapters coordinate usage of the memory buffers by respective devices.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and asynchronous interrupt service. The VLSI device has a plurality of processors which cooperate for generating video signal streams and at least one and preferably at least two interrupt registers for controlling the operations of instruction data stream execution and interruption.

Abstract: To enable a computer system such that each local arbiter is supposed to output its own priority as the right to use the bus on a common arbitration bus through open-collector-type drivers to determine a winner in arbitration, to expand the bus by way of a channel different from bus signal lines. Certain representation features 73 and 79 having the functions of a local arbiter that represent the arbitration level of the other bus are provided in both a primary system and a secondary system linked via a channel in a signal transmission mode different from the signal transmission mode of the bus. Arbitration is first conducted on each of the buses of the primary and secondary system to determine winners in arbitration. Notification of the arbitration level of each winner is made through a channel to the representation feature on the other bus.

Abstract: A bridge is provided between an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus and performs memory cycles on both buses simultaneously when a master on the ISA bus initiates a memory transfer. Data is steered between the ISA and PCI buses when a slave on the PCI bus claims the memory address within a predetermined time period after the memory cycle is initiated on the PCI bus. The ISA bus is isolated from the PCI bus when no slave on the PCI bus claims the memory address. This allows the memory cycle to be completed on the ISA bus, and the memory cycle on the PCI bus is terminated.

Abstract: A computer system that has a processor that services interrupts in response to receipt of a signal at the interrupt request has a first device and a second device coupled to the processor. The first device is capable of transmitting a first interrupt request signal that includes an edge transition. The second device is capable of transmitting a second interrupt request signal that comprises a level assertion. An interrupt handler is coupled to the processor and the first and second devices, the interrupt handler receiving the first and second interrupt request signals as inputs and providing the first and second interrupt request signals as outputs to the processor in a sequence according to a predetermined criteria, the first and second interrupt request signals having identical priority.

Abstract: An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.

Abstract: Television viewers are presented with the opportunity to be diverted during intervals such as display of commercials, delays pending initiation of a near video on demand signal stream, and the like. The diversions take the form of overlaying on a frozen or continuing moving frame of visual images various game playing constructs manipulable by the remote control used to perform other control functions for the display device. The display device may be a television receiver linked to a set top device, an intelligent television receiver, or a personal computer provided with television image reception and display capability. Overlaying occurs over a frozen frame in certain disclosed diversions and over moving images in others. The accompanying audio signal stream may also be modified.

Abstract: A computer system having four states of power management: a normal operating state, a standby state, a suspend state, and an off state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. The normal operating state and the off state correspond to the typical on and off states of more conventional computer systems.

Abstract: An information handling systems capable of transferring data among various system resource devices such as input/output (I/O) devices and a system memory includes a first bus coupled to the system memory, a second bus coupled to the system resource devices, and a bus interface unit (BIU) coupled between the first bus and the second bus. Each of the system resource devices is capable of controlling the second bus after arbitrating therefor. The BIU includes a buffer for temporary storage of data being transferred between the first bus and the second bus, and control logic for generating a lock control signal, after one of the system resource devices has gained control of the second bus by arbitration, to gain control of the first bus to prevent other system resource devices from accessing the first bus. The control signal is dynamically generated by the BIU based on programmable conditions relating to the data transfer, thus optimizing data transfers between the first bus and the second bus.

Abstract: Packaged signal muting circuits (e.g. on primed circuit cards or boards), route pulse signals with very short rise times from a lossy driver to multiple devices. In these routing circuits, a complex network of conductors branches from a common junction adjacent the driver output into multiple (in the disclosed embodiment, three) conduction paths of unequal length. In accordance with the invention, the internal impedance of the driver is matched to the aggregate characteristic impedance of the branch paths, and a loss less compensating circuit is attached to a shortest branch path. The compensating circuit is designed to transfer signal reflections of predetermined form to the branching junction at the driver via the shortest branch.

Abstract: The present invention provides a program that creates a preliminary map of a multiple bus network used to connect peripheral devices to the central processing unit of an information handling system. This preliminary map is then used by configuration software of the information handling system to locate the peripheral devices in the multiple bus network to configure them. If the physical configuration of the multiple bus network should change in any way, the inventive program can make corresponding changes in the preliminary map without having to rewrite or change the program.

Abstract: A video display, which may be a television receiver with associated set top device, an intelligent television receiver, or a personal computer system enabled for television display, has associated therewith a remote control which controls modification of the visual images displayed. By use of the remote control, a human observer may cause a processor controlling the video display to execute a control program formulated in a particularly concise language and controlling the display of menus and the like. Menus are displayed as overlays onto a live motion video image.