Abstract: Body-worn antennas operate in combination with a direction finding processor to be able to detect the presence of electromagnetic radiation involved in communication as well as the direction of the source of the electromagnetic radiation. In one embodiment, a number of wide bandwidth antennas, 2 MHz to 40 GHz, are incorporated into a body-worn vest or garment such that an individual wearing the vest is being provided with a wearable system for indicating the direction of the source of incoming signals. If the orientation and geographic location of the individual are known via the use of a compass and/or by GPS receiver, the source of the radiation can be pinpointed by triangulation with inputs from other body-worn units. For omni-directional detection, pairs of antennas are provided with feed points or spigots which are fed in phase.

Abstract: A system is provided for assisting in the detection and tracking of narrowband signals arriving at an antenna array operating over a wide detection bandwidth and in a crowded RF environment. Since the nature of the detection mission is constrained to be a general search, the system does not attempt to detect signals of interest via matched filtering mechanisms (i.e. training sets), but exploits general properties such as power, frequency, time and angle of arrival. For the purposes of providing sufficient Frequency/Time resolution as well as to avoid array overloading in the detection process, the digitized wideband streaming data is frequency channelized using a sufficiently high revisit rate for the signal set of interest, constrained by the required feature detection accuracy or environment adaption rates. Within each frequency subchannel, efficient array signal subspace tracking techniques are used to separate and track spatially separated cochannel signals.

Abstract: A dual uncoupled mode box antenna which includes a conductive bottom horizontal ground plane, and a box structure superimposed on this ground plane. The box structure includes a vertical first conductive side insulated from the ground plane, and a vertical second conductive side insulated from the ground plane positioned in gapped relation to the first side. There is also a vertical third conductive side which is grounded to the ground plane and which is positioned in perpendicular gapped relation to second side. A vertical fourth conductive side is also grounded to the ground plane and is positioned in perpendicular gapped relation to the first and third sides. A conductive top is superimposed over and insulated from the first, second, third, and fourth sides. The first and second sides are fed in quadrature to create either left handed or right handed polarization.

Abstract: A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly.

Abstract: An active armor system, which includes a first armor layer and a second armor layer. An interior space is interposed between the first and second armor layer. A third layer is also positioned preferably adjacent to and on the inner side of the first layer This third layer is comprised of a material selected from a piezoelectric material, and electrostrictive material, and a magnetostrictive material. The third layer may also be characterized as any material capable of producing an electrical or magnetic field within the space in response to the application of mechanical force on this third layer. The application of force on the third layer as a result of the impacting of a shaped charge projectile on the first armor layer will result in the production of an electric or magnetic charge in the interior space which will disrupt the formation of the shaped charge gas jet so as to prevent the penetration of the second armor layer.

Abstract: A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

Abstract: A method for forming a resistor includes causing a semiconductor layer to have a first resistance, forming a first mask on the semiconductor layer, causing portions of the semiconductor layer left exposed by the first mask to have a second resistance that is lower than the first resistance, forming a second mask on the first mask and on the semiconductor layer, removing portions of the first mask and the semiconductor layer left exposed by the second mask, removing the second mask, and causing portions of the semiconductor layer exposed by the removing of the second mask to have a third resistance that is lower than the second resistance. Because a resistor formed by such a process can include an aligned body and contact, it often occupies a smaller area than prior integrated resistors having a similar resistance value.

Abstract: A wideband meander line loaded antenna is provided with a capacitive feed to lower the reactance of the meander line antenna such that at lower frequencies the antenna reactance goes negative to cancel out the reactance of the meander line and distributed capacitance. The resultant lowering of the low frequency cut-off for the antenna permits the antenna to be used, for instance, in cellular phone applications in which not only are the cellular frequencies accommodated by the antenna, but also PCS and GPS frequencies as well. With the capacitive, feed the low frequency cut-off is lowered by as much as 30% over standard meander line loaded antennas.

Abstract: A system is provided for reducing the time that a ship must be maintained on station to collect calibration data by reducing the frequencies at which calibration data is to be collected. Since it is impractical to consider calibrating over elevation angle and polarization on the full-scale ship, an accurate scale model and test facility are utilized, with surface wave data being collected from the ship before model-based data can be utilized. In the subject system, the number of calibration frequencies used aboard ship is dramatically reduced by as much as 80%, thus reducing the time the ship must be on station when doing a calibration run. In one embodiment, the shipboard surface wave data for one elevation and one polarization is combined with surface wave and sky wave data from the scale model to generate an array manifold or database used in subsequent direction finding activities.

Abstract: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region.

Abstract: A method for fabricating resistors within a semiconductor integrated circuit device is disclosed. A resistor is fabricated by first depositing a passivation layer on a semiconductor substrate having multiple transistors previously formed thereon. Next, a first contact window and a second contact window are formed through the first passivation layer at a first contact location and a second contact location, respectively. The first and second contact windows are then filled with metal, such as tungsten, and the metal at the first and second contact windows is planarized to form a first bottom contact and a second bottom contact, respectively. A resistive film, such as polysilicon, subsequently deposited over the first passivation layer. Next, a second passivation layer is formed over the resistive film. Finally, a first top contact and a second top contact are formed to respectively connect the first bottom contact and the second bottom contact to the resistive film.

Abstract: An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and possibly structurally equivalent, and are coupled to receive input signals spanning redundant input signal sets. A given logic structure within the first logic element may receive specified input signals within a particular input signal set, while an analogous logic structure within the second logic element may receive corresponding input signals within the counterpart input signal set. A radiation induced transient pulse that affects one input signal may affect an output signal asserted by one logic structure; however, since the transient pulse doesn't affect a corresponding input signal applied to the analogous logic structure, the dual path logic gate may output at least one correctly valued signal when a transient pulse occurs.

Abstract: A method for growing solid state laser crystal boules is disclosed that when made into laser rods do not need separate end caps attached to the laser rods. The crystal boule is grown as a single integral unit with three segments. Two segments, the end segments, are un-doped or non-laser active, and they flank a central segment of the boule that is doped with an active laser ion. A first end segment of the crystal boule is first grown from un-doped melt material in a first crucible by slowly withdrawing its growing end from the first melt. The boule is then transferred to a doped melt in a second crucible where its growing end is submersed therein to grow the doped, laser active central segment. The temperature of the melt in the second crucible is initially higher than the growing temperature of the first melt and causes the growing end of the boule to melt.

Abstract: A single-event upset immune flip-flop circuit is disclosed. The single-event upset immune flip-flop circuit includes a first single-event upset immune latch and a second single-event upset immune latch. The first single-event upset immune latch has two inputs and two outputs. The second single-event upset immune latch also has two inputs and two outputs. The two inputs of the second single-event upset immune latch is connected to the two outputs of the first single-event upset immune latch. The state of the first single-event upset immune latch changes only when the signal polarities at both inputs of the first single-event upset immune latch are identical. Similarly, the state of the second single-event upset immune latch changes only when the signal polarities at both inputs of the second single-event upset immune latch are identical.

Abstract: A method of fabricating a dense pixel array comprising the steps of: (a) printing a photoresist mask and applying said mask to a semiconductor material substrate to form a masked area and an unmasked area on said substrate; (b) applying a photoresist material layer to the unmasked area of the substrate, then applying a metal layer over the photoresist material layer and the substrate, and then applying a solvent to remove the photoresist material layer and said metal layer applied over said photoresist material layer to leave a plurality of metal layers superimposed over the unmasked area of the substrate; (c) removing the substrate to a depressed substrate surface between the metal layers formed in step (b) to form a plurality of pixels each having an upper metal layer; (d) superimposing an insulative layer over each of the metal layers formed in step (c); (e) forming a hole in at least one of the insulative layers formed in step (d) so as to expose the metal layer under the insulative layer; and (f) superim

Abstract: A system is provided for detecting the presence of two or more acoustic sources or targets such as vehicles that are traveling between an array of unattended passive ground sensors, in which the sensors each include a phased-array microphone and processing to determine the bearing to the acoustic target. The bearings from pairs of these sensors are subtracted one from the other to provide a bearing line difference “delta” which is the indicator of the presence of an acoustic target close to the line between the two sensors of the pair. A tripwire threshold indicating the presence of a target is set when the absolute value of this bearing line difference “delta” is greater than, for instance, 150°, with the “delta” being 180° when the target is on the line between the two sensors.

Abstract: A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.

Abstract: A fast deployment and retrieval system permits the rapid deployment of a decoy in seconds in response to an incoming threat, thus eliminating the necessity of pre-deployment, with retrieval permitting reeling in and deployment of the decoy a number of times during a mission in response to threats, and a commensurate reduction in life cycle cost. Upon detection of an incoming threat by a warning receiver, a controller coupled to a transmission releases a brake that is utilized to control the speed of deployment, whereas upon retrieval, the transmission drives a motor for retrieval of the decoy. The system is thus reusable, fast reacting, and also minimizes range penalty considerations because the decoy is only deployed when needed. In one embodiment, the system accommodates both a towing cable and a fiber-optic signal cable in which apparatus for unwinding of the cables is mechanically ganged together so that the cables pay out at the same rate.

Abstract: An apparatus for providing mechanical support to a column grid array package is disclosed. The column grid array package uses solder columns to provide electrical connections between a ceramic substrate and a printed circuit board. The ceramic substrate has two sides, with an integrated circuit chip mounted on one side and many input/output pads mounted on the other side. Solder columns are attached between the input/output pads and the printed circuit board. A corner post is located at each corner of the column grid array package to secure the position of the ceramic substrate in relation to the printed circuit board.

Abstract: An inexpensive, small, low-power consumption, wide-band, high resolution spectrum analyzer is provided as a listening device for throw-away applications such as surveillance that involve deployment of large numbers of battery-powered spectrum analyzer modules to detect a signal source such as two-way radio traffic. Power requirements are minimized by the utilization of only one chirp generator to elongate battery life while providing a high resolution result. In order to minimize power drain the spectrum analyzer includes a single compound-chirp Fourier Transform generator. The compound chirp generator is used in one embodiment with a surface acoustic wave, SAW, dispersive delay line in conjunction with a surface electromagnetic wave, SEW dispensive delay line.