Abstract: A piezoelectric component-mounting foil and foil making method are disclosed, whereby a first portion of the foil in a first plane substantially parallel to a second portion of the foil in a second plane are connected by a central portion not in the first or second plane, the central portion having at least one width dimension of the central portion less than at least one length dimension of the central portion. A conductive foil material, appropriate thickness, overall geometry, and, if desired, appropriate notch configuration are selected for a desired implementation of the foil for conductively attaching and at least partially supporting at least one piezoelectric component such as a quartz crystal.

Abstract: A two wire modem selects a carrier frequency in a baud rate from a predetermined plurality of carrier frequencies and baud rates to communicate with another modem over a communication media in a full duplex mode based on signal and echo characteristics of the communication media estimated by the modem. In addition, the processes of estimating channel characteristics and estimating range are combined in a common start up procedure comprising a plurality of successive time segments for a call modem to communicate with an answer modem over a communication media. Still further, a method is provided for switching from a primary communication media connection to a secondary connection of a data communications network for communication by first and second modems coupled to the network. More specifically, when a failure is detected in the primary connection, the secondary connection is qualified before switching thereto.

Abstract: The present invention includes an apparatus and a method for transceiver self-diagnostic testing in a communication system. A feedback unit (228, 326) is utilized that allows performance of a loopback test independent of a transmit frequency to receive frequency difference without undue proliferation of circuitry.

Abstract: A variable length string matcher finds the longest string in a stored sequence of data elements (e.g., in a history buffer) that matches a string in a given sequence of data elements. The matcher includes circuitry that operates iteratively to compare data elements of the strings and determine the longest matching string based on when an iteration does not result in issuance of a match signal. In another aspect, the history buffer is an associative content addressable memory (CAM), and the string matcher uses absolute addressing of the CAM to determine the longest matching string.

Abstract: Interdigitation and surface mounting of a block filter that has at least a first resonator and that has at least a first pole and at least a first zero in its transfer function provides a surface mountable block filter having selectable frequency rejection response operation.

Abstract: An apparatus and method (200) for providing a hybrid circuit assembly carrier bracket are included wherein the bracket is constructed and arranged to provide controlled placement of at least a first power transistor (124, 126) and to provide a highly efficient thermal transfer and dissipating arrangement. The bracket is constructed and arranged to provide for placement of at least a first substrate for a hybrid circuit assembly thereon, and includes at least a first power transistor aperture (120, 122) with at least two bracket projections (146, 148) for permitting placement of said transistor on plural electrical contacts (104, 106). The heat generated by components on the circuit board(s) is transferred and dissipated substantially by biasing at least one bracket projection member resiliently against a heat sink (108, 110, 112, 114, 116, 118).

Abstract: A device and method utilize a linear feedback/feedforward configuration to estimate and cancel a listener echo wherein equalizer (202) and listener echo cancellation (204 and 208) units are jointly updated, allowing determination of an error signal once (204 and 208), in place of the former method of separate error signal determination for each of an equalizer and a listener echo canceller. An improved phase-correction scheme is utilized to compensate the frequency offset in the listener echo. The relationship between the listener echo and talker far echo is utilized to facilitate the listener echo cancellation.

Abstract: A high-speed processor utilizes combinational logic and range limitation for a modified input value to increase efficiency in convergence factor determination for convergent division and square root computation. An input value is modified to a value in a limited range, which is then partitioned into two subdivisions. By utilizing these two groupings, the processing platform minimizes time consumption in conversion factor determination by inverting selected binary bits to form a modified factor and utilizes that modified factor to facilitate high-speed convergence factor computation.

Abstract: A logarithm of an input value is computed utilizing a function generator to generate a first logarithm of an approximation value of the input value, scaled to a natural logarithm value where the first logarithm is not a natural base logarithm, and then combined with a correction value, obtaining a natural base logarithm of the input value. An error value, related to the input value and the approximation value, is generated and is utilized in a specified power series to determine the correction value. The natural base logarithm obtained is scaled by a natural base logarithm of a desired base of a desired output logarithm, thereby determining the desired output logarithm of the input value that has the desired base.

Abstract: Optimal baud rate and carrier frequency for data transmission using a modem on a communication channel (100) are determined by utilizing an on-line line probing technique. The technique utilizing the information from a decoder noise power spectrum estimated from the equalized received modulated signals and decoder output symbols to determine the decoder signal-to-noise ratios (SNRs) and supported bit rates for the available baud rates and carrier frequencies. These SNRs and bit rates together with a band edge SNR difference at each frequency band are utilized to select (110) the optimal baud rate and carrier frequency.

Abstract: Automatically restoring data transmission by monitoring line degradation and switching to a new line (or lines) when line quality falls below a prescribed standard. Data transmission is maintained on the leased line while communication is being established on the dial line, so as not to disrupt data transmission; communication is established across two dial lines to restore full-duplex transmission; energy is maintained on the dial lines at times when data is not being transmitted to prevent a change of channel on a dial line; a signal processor, associated memory, and analog interface circuitry provide the data restoral functions; control of the restoral procedure is handled by one modem (e.g., the calling modem), and commands are sent to the other modem over either the leased or dial lines.

Abstract: Measuring the programming resistor in a data jack by placing the resistor in an AC voltage divider circuit via a transformer. An AC voltage (preferably generated by the modem's own transmitter circuitry) is applied to the voltage divider circuit, and an AC voltage measurement (preferably made by the modem's A/D converter) provides the resistance of the programming resistor. Matching the low-pass filter impedance characteristic of a local loop with a network having a matching low-pass filter characteristic, while also compensating the received signal with a compensation network having a high-pass filter characteristic, to reduce the frequency dependent gain effects caused by the matching network and/or the local loop.

Abstract: A first set of plated-through holes in the printed circuit board (PCB) are covered by a protective solder mask on the solder side of the PCB while a second set of plated-through holes are exposed. Electrical components are disposed on the component side with leads inserted in the second set of holes. Solder is prevented from flowing into the first set of holes during wave soldering by the mask covering. Conductive pins designed for press fitting into the first set of holes are inserted therethrough to define connecting pins on each side of the PCB following wave soldering. This permits both a wave soldering and press fit operation to be accommodated.

Abstract: A self-adjusting phase-locked loop (PLL) parameter adjusting device (APAD) (100) and method that automatically adjusts a phase-locked loop to provide tracking ability when and where needed, as opposed to utilizing a PLL adjusting device with preset parameters, thus maintaining minimal possible noise bandwidth. The method utilizes (1) successively integrating the PLL error output signal over a number of samples to provide a plurality of sums, (2) checking a predetermined number of sums and recording and counting the sign of each sum, (3) comparing the counted record to a predetermined threshold value, and (4) automatically adjusting PLL parameter(s) and the sample number in accordance with a predetermined strategy, such that adjusted PLL parameters are provided to the PLL.

Abstract: A device (800) and method (900) are included for providing a high-rate queueing discipline in an information network system having a plurality of traffic classes. The high-rate queueing discipline is based on a scan table-based dequeueing scheme having a scan table that is precomputed and stored in memory, thus facilitating rapid processing of different traffic class information. The device and method are particularly useful in a fast packet system.

Abstract: A device and method for asynchronous cyclic redundancy checking (CRC) for digital receivers includes utilizing a finite impulse response (FIR) filter, and comparing and gating circuits. The FIR filter may contain a first multiple delay system unit (102) and a first logic gating system (104). The comparing and gating circuit may contain a second multiple delay system unit (106), and a second logic gating system (110). The device and method is implementable, where desired, utilizing a computer program. The invention provides a faster determination of a CRC frame synchronization on a received digital signal.

Abstract: A device (400) and method (1200) include interleaved trellis precoding to provide a low probability of error in the presence of bursty noise. The use of interleaving and shaping, particularly in a trellis precoded system, provide for improved burst error bit correction.

Abstract: Arbitration is performed among a plurality of users for access to a shared resource in a system of the kind in which the users arbitrate by placing arbitration signals on a line and subsequently comparing their arbitration signals with a signal appearing on the line, by providing the users with independently operating clocks, and controlling the progression of the arbitration based on timing provided by the clock of at least one of the users. The progression of the arbitration thus does not depend upon a single master clock, or upon synchronizing the individual user clocks.