Abstract: Methods, devices, computer program products and systems for contact matching that is based on changing the dial string to include or delete codes. The described aspects provide for contact matching and subsequent display of contact information to occur in most instances in- which a connection occurs and for no matching and no subsequent display of contact information to occur in most instances in which a connection does not occur. The described aspects, systems and apparatus overcome problems related to an exact match scheme, which fails to provide contact information in many instances in which a call connection occurs, and a last, seven, or any other number, digit match scheme, which may provide contact information in instances in which a call connection cannot he made or is made to an unintended device.

Abstract: The basic idea of the present invention is to specify at least two different triggers for sending a measurement report from the mobile station to the network. According to the invention, the network specifies the triggers to be used in different measurement report types. The triggers are preferably upper or lower threshold values for parameters of the radio signal. In response to having detected that the measured value has exceeded its upper threshold value or gone under its lower threshold, the mobile station sends the network a measurement report.

Abstract: A method of signal reception according to one embodiment of the invention includes receiving a set of data values over a first frequency band during a first time slot, and receiving another set of data values over the first frequency band during a second time slot which is after the first time slot. Between the first and second time slots, the method includes sampling a signal received over a second frequency band and storing the samples. Based on the samples, a received signal quality value is calculated.

Abstract: Techniques are provided for reducing the likelihood of missed pages during cell reselection. For cell reselection with early camping, a terminal determines that reselection from a first base station to a second base station is required. The terminal then performs cell reselection and receives sufficient system information to process a paging channel for the second base station. The terminal starts monitoring the paging channel upon receiving this information and prior to completing the cell reselection. For cell reselection with reconfirmation, the terminal receives and decodes a control channel for the second base station prior to performing cell reselection. For cell reselection with overlapping page reception, the terminal monitors the paging channel for the first base station until a terminating event occurs and starts monitoring the paging channel for the second base station upon receiving sufficient system information. The monitoring of the two paging channels overlaps in time.

Abstract: An information processing system includes an operation speed adjustable processor, and is adapted so that, with increase of operation speed of the processor, its performance is improved and power consumption is increased. The system comprises a scheduling unit for carrying out a processing to determine task of which processing should be executed at respective time points to shift control right to the task in accordance with the determination result, a power management unit periodically activated to carry out prediction of the power consumption of the processor and setting of operation frequency thereof, and a satisfaction degree evaluation unit activated in response to request from a scheduling module to evaluate the relationship between respective tasks and satisfactory services provided by them. Accordingly, it is possible to suppress operation frequency of the processor within the range that the satisfaction degree permits thus to carry out power saving.

Abstract: When a request processing unit 2a receives processing request including memory access, it executes processing in accordance with the request, and when memory access takes place, it outputs access request to address designated by the processing request. A memory access proxy unit 2b sets memory protection information 1a of object 1 at a memory management unit 3a to output memory access instruction to a processor 3. The memory management unit 3a generates exception when memory access instruction from the memory access proxy unit 2b is access except for area set as memory protection information 1a. Thus, it is possible to carry out, at high speed, with high reliability, memory access such that, in accordance with request of an object, other object executes.

Abstract: The present invention relates to an information processing apparatus wherein a device connected to a host computer enters a sleep mode in accordance with a judgment made by the device itself, and the device is restored to its original operating state by a hardware reset signal received from the host computer. To put it in detail, if no data is exchanged through an ATAPI command data I/F for at least a predetermined period of time, a CPU of the device outputs a sleep mode to a clock generator and a drive power supply block to put the device in a sleep mode. When a CPU of the host computer outputs a HRST signal in this mode to the device through an ATAPI bus to restore the device from the sleep mode, an IRQ signal reception unit of the CPU employed in the device receives this HRST signal. Receiving the HRST signal, the CPU of the device issues a command requesting restoration from the sleep mode to the clock generator and the drive power supply block.

Abstract: To enable setting for transmission through network such as IEEE1394 system with input plugs freely, when transmitting data obtained in an output device connected to a predetermined network to the network from a predetermined output plug of the output device and receiving that data through a predetermined input plug of an input device connected to the network, the output device confirms an address of a buffer for storing data obtained in the input plug of the input device temporarily prior to start of data transmission, according to an address set in a predetermined pointer within a register constituting the input plug and then, transmits data from the output device to the confirmed address.

Abstract: A picture signal processing method and apparatus in which the block distortion as well as the mosquito noise produced on encoding/decoding a picture is to be suppressed. The picture signal processing apparatus includes a filter for filtering a picture, an encoder 5 for block-encoding the picture, a decoder 13 for decoding an encoded picture from the encoder 5 and a noise reducing unit 14 for reducing at least the block distortion of a picture decoded by the decoding unit 13 to reduce the noise otherwise produced on encoding/decoding the picture.

Abstract: A carrier reproduction circuit comprising a complex multiplier circuit for generating a first signal by detecting a difference between a received signal and a signal fed back at a Costas loop circuit, a loop filter circuit for generating a second signal by processing the first signal by using a first integration loop containing a first delay circuit for giving one-symbol's worth of a delay, and an NCO circuit for feeding back the signal generated by processing the second signal by using a second integration loop containing a second delay circuit for giving one-symbol's worth of delay toward the complex multiplier circuit and switching the loop filter circuit and the NCO circuit to a state 12 symbols before in accordance with a TMCC detection signal and thereby capable of performing the carrier reproduction of the received signal at a high speed and with a high precision.

Abstract: There are provided a storage device for outputting-data in such a manner that whether or not error correction has been made can be discriminated, and a data processing system in which a storage device finishes data to a data processing device in such a manner that whether or not the area management information has been corrected for errors can be discriminated and in which the data processing device discriminates whether or not the area management information has been corrected for errors in order to perform predetermined data processing. There is also provided a data processing method for the storage device and for the data processing system.

Abstract: The invention relates to a coding apparatus for embedding second data into first data without deteriorating the first data and a decoding apparatus for decoding coded data into original first data and second data without deteriorating those data. The invention provides a coding apparatus which has a memory for storing at least partial data of first data, and embeds second data into the first data by rearranging, according to the second data, the at least partial data of the first data that is stored in the memory. The invention also provides a coding apparatus for decoding coded data in which second data is embedded and at least partial data of the coded data has been subjected to rearrangement by using one of a plurality of rearrangement patterns. The decoding apparatus calculates correlation between adjacent data for each rearrangement pattern, and decodes the original first data and the second data according to a rearrangement pattern that is determined based on the correlation.

Abstract: Voice synthesis with improved expressivity is obtained in a voice synthesiser of source-filter type by making use of a library of source sound categories in the source module. Each source sound category corresponds to a particular morphological category and is derived from analysis of real vocal sounds, by inverse filtering so as to subtract the effect of the vocal tract. The library may be parametrical, that is, the stored data corresponds not to the inverse-filtered sounds themselves but to synthesis coefficients for resynthesising the inverse-filtered sounds using any suitable re-synthesis technique, such as the phase vocoder technique. The coefficients are derived by Short Time Fourier Transform (STFT) analysis.

Abstract: A GCA+ADC chip 23 on a main circuit board 20 is supplied with an image signal from a CCD circuit board 1 via an input terminal 21 connected to a line 16. Concurrently, the GCA+ADC chip 23 is supplied with a specified DC reference signal REF 13 from the CCD circuit board 1 via an input terminal 22 connected to the other line 17. An internal operation subtracts the DC reference signal REF from the image signal. Drivers 9 and 10 are provided with the same characteristics. If an interfering noise is picked up during transmission, these signals carry the same contents on respective transmission. This interfering noise is canceled during the subtraction inside the GCA+ADC chip 23.

Abstract: A data recording and reproducing apparatus having a recording and reproducing means for recording and reproducing data containing video data and/or audio data to and from a record medium that is non-linearly accessible and a plurality of input and output processing means for accessing the recording and reproducing means in respectively assigned time slot periods, outputting the data that is output from the outside to the recording and reproducing means, and inputting the data from the recording and reproducing means is disclosed, that comprises an operating means for performing at least a record operation for causing the data to be recorded to the record medium and a reproduction operation for causing the data to be reproduced from the record medium, and a displaying means for displaying the data that is input to and that is output from the plurality of input and output means, wherein the operating means and the displaying means are integrally structured.

Abstract: An encoder to encode video streams representing a moving picture is provided whose video encoder calculates a bit storage quantity an STD video buffer should have when input of a stream ending with a first picture to the STD video buffer ends, calculates an initial bit storage quantity of a second picture of a stream concatenated to the end of the first picture and starting with the second picture, in a VBV buffer, based on the calculated bit storage quantity of the STD buffer, and encodes the stream based on the bit storage quantity. The video encoder further calculates a bit storage quantity of the STD video buffer, for decoding a picture of the stream in the STD video buffer, calculates, based on the calculated bit storage quantity, a bit storage quantity the VBV buffer should have for ending decoding of a fourth picture of a second stream concatenated to the beginning of a third picture and ending with the fourth picture, and encodes the stream based on the calculated bit storage quantity.

Abstract: An information processing apparatus, disposed between a controlling portion and hardware, for performing a process corresponding to a program that contains capsulated process portions for controlling the hardware in response to messages received from the controlling portion. The program includes a first process portion for communicating with the controlling portion; a second process portion for communicating with first and second hardware; a third process portion for communicating with the first process portion and the second process portion and executing an interfacing process corresponding to the first hardware; and a fourth process portion for communicating with the first process portion and the second process portion and executing an interfacing process corresponding to the second hardware. The first process portion outputs a message to either the third process portion or the fourth process portion corresponding to a message received from the controlling portion.

Abstract: The present invention provides a data processing method and apparatus capable of shortening the processing time required when editing previously encrypted track data. An example of a transfer of audio track data between a portable player and a storage device is provided. The track data is comprised of one or more parts, each of which in turn is comprised of a series of data blocks. Each block of the track data is encrypted prior to transfer using a block key. The block keys are determined in such a manner that subsequent editing of the track data which results in redistribution of the parts does not require full decryption of the data.

Abstract: Skipping reproduction of image data is performed while maintaining the continuity of a moving image before and after a skipping point, thereby preventing the video buffer in the decoder from failing. A moving image recording and reproducing apparatus for such skipping reproduction includes a decoder to decode an MPEG-2 video stream recorded on an optical disc and an encoder to re-encode the decoded video stream by editing. A multiplexer multiplexes the edited video stream and an audio stream, and an analysis controller controls the editing. To generate a multiplexed stream which can be reproduced by skipping from a first video stream to a second video stream, the analysis controller limits the re-encoding so that the bit occupancy in the video buffer is smaller than the capacity of the video buffer and larger than zero for a time period starting with the supply of the second video stream to the video buffer of the decoder and ending with the beginning of the decoding of the second video stream.

Abstract: The object of the present invention is to convert a signal from an arbitrary equipment into a signal at a data rate for used in a device. A semiconductor memory (7) is controlled by a control signal from a memory control section (8), thereby repeatedly reproducing recorded still image signals each corresponding to one frame. If a reproduction signal has a data rate of 4:4:4, the reproduction signal is supplied to a rate conversion circuit (9) for converting the data rate into 4:2:2 or 4:1:1. A digital video signal thus converted is supplied to a VTR section (6) through a change-over switch (5). One of the digital video signal from the rate conversion circuit (9) and the reproduction digital video signal from the VTR section (6) is selected by a switch (10). The selected digital video signal is supplied to a D/A conversion circuit (11) and fetched a digital output terminal (12).