Abstract: A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge.

Abstract: A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.

Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

Abstract: A method is provided of forming contact vias. A dielectric region is formed to overlie substantially all of a transistor structure, the dielectric region having a substantially planar upper surface. A dielectric barrier layer is formed to overlie the upper surface of the dielectric region, the dielectric barrier layer being adapted to substantially prevent diffusion of one or more materials from above the dielectric barrier layer into the dielectric region. A first contact via is formed to extend through the dielectric barrier layer and the dielectric region to provide conductive communication with a conductive member of the transistor structure. A second contact via is formed to extend through the dielectric barrier layer and the dielectric region to provide conductive communication with one of a source region or a drain region of the transistor structure.

Abstract: A method is provided of forming a contact to a semiconductor structure. A current-conducting member is formed which extends horizontally over a first portion of a semiconductor device region but not over a second portion of such semiconductor device region. A first film is formed which extends over the second portion and only partially over the member to expose a contact portion of the member. A first contact via is formed in conductive communication with the contact portion. The first contact via has a silicide-containing region self-aligned to an area of the member contacted by the contact via. A second contact via is formed in conductive communication with the second portion, the second contact via extending through the first film.

Abstract: An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.

Abstract: An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent to the channel region. A first stressed region having a first type of stress is provided to underlie the channel region, in which the first type of stress is either compressive type or tensile type. Second stressed regions having a second type of stress are provided to underlie the source and drain regions, in which the second type of stress is an opposite one of the compressive type or tensile type stress of the first stressed region.

Abstract: According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference potential. Each trench capacitor includes a node dielectric and a node conductor formed within the trench. Buried plate (BP) diffusions extend laterally outward from a lower portion of each trench of the array, the BP diffusions merging to form an at least substantially continuous BP diffusion region across the array. An isolation region extends over a portion of the BP diffusion region. A doped well region is formed within the substrate extending from a major surface of the substrate to a depth below a top level of the substantially continuous BP diffusion region. An electrical interconnection is also provided to the well region.

Abstract: A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first dopant including at least one of an n-type dopant and a p-type dopant is then implanted to a second depth into portions of the amorphized semiconductor region not masked by the first gate conductor to form source/drain portions adjacent to the channel portion. The substrate is then heated to recrystallize the channel portion and the source/drain portions of the amorphized semiconductor region. After the heating step, at least a part of the recrystallized semiconductor region is locally heated to activate a dopant in at least one of the channel portion and the source/drain portion.

Abstract: An integrated circuit is operable to measure tolerance to jitter in a data stream signal. A Clock And Data Recovery Circuit (“CDR”) thereon recovers a phase of a clock for sampling a data stream signal containing a repeatable known sequence of data values and then samples the data stream signal with the recovered clock phase to obtain data stream sample data. An error rate determination circuit independently generates the repeatable known sequence of data values and compares them with the data stream sample data to determine an associated error rate. A control circuit coupled to the CDR delays the recovered clock phase by a predetermined amount a plurality of times and monitors the error rate after each time it delays the recovered clock phase. In this way, a maximum delayed clock phase is determined, representing a right timing signal margin for which the data stream signal can be sampled.

Abstract: Systems are provided for generating and distributing a plurality of reference currents on an integrated circuit. More particularly, an integrated circuit is provided which includes a reference current generating system. The reference current generating system includes a first reference current generator disposed at a first location of the integrated circuit which is operable to generate a plurality of first reference currents. A plurality of second reference current generators are disposed at a plurality of second locations of the integrated circuit. Each of the second reference current generators are operable to generate a second reference current from one of the plurality of first reference currents. In a particular example, the first location at which the first reference current generator is disposed is a central location and the second locations are disposed remote from the first location.

Abstract: A method of manufacturing a semiconductor trench device comprises forming a dielectric on a substrate, the dielectric having an underlying oxide layer adjacent the substrate, etching a trench in the dielectric and the substrate, forming a recess in the underlying oxide layer, filling the recess with a nitride plug, filling the trench a conductive material and oxidizing the dielectric and the conductive material, wherein the nitride plug controls a shape of a corner of the trench.

Abstract: A direct sensing circuit and method for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation. Prior to the data read operation, both the bitline and the data line are precharged to precharge voltages and a sense node is precharged to ground. A pFET device has its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and has its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device. An nFET device has its gate coupled to the sense node to detect and amplify the signal level thereof, and has its drain coupled to the data line.

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.

Abstract: A method and structure for an integrated circuit chip includes storage devices, isolation regions adjacent the storage devices and surface straps connected to the storage devices, wherein the isolation regions have a border coincident with the surface straps.

Abstract: An integrated circuit memory device comprising an arrangement of physical wordlines, WL0-WLn, arrange such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, and such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession. The ternary results A, B or C are used to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline. Preferably, the ternary results A, B and C are respectively encoded by said binary states of said pair of logical row address bits, said binary states being “00,” “01,” and “10” respectively.

Abstract: A method of forming a wiring pattern in a device comprises forming an array of grooves in a mask, forming first spacers adjacent vertical walls of the grooves, removing the mask, forming second spacers adjacent the first spacers, and filling areas between the first spacers and areas between the second spacers with a material to form the wiring pattern.

Abstract: A method of fabricating a semiconductor device in which the bitlines and the bitline contacts are fabricated utilizing a single masking step in which line-space resist patterns are employed in defining the regions for the bitlines and the bitline contacts. The method utilizes a first line-space resist pattern and a second line-space resist pattern which is perpendicularly aligned to the first line-space resist pattern to form bitlines that are self-aligned to the bitline contacts.

Abstract: A method for providing dual work function doping and borderless array diffusion contacts includes providing a semiconductor substrate, a gate insulator, a conductor on the gate insulator, an insulating cap on the conductor and insulating spacers on sidewalls of a portion of the conductor and the insulating cap. The method also includes doping portions of the semiconductor substrate and the conductor with a first conductive type and other portions with a second conductive type. The conductor may be annealed such that dopants of the first and second conductive types spread over the respective conductors.