Abstract: The present invention provides a method and an optical lithographic system which eliminates the standing wave effect typically observed in photoresists without the need for altering the thickness of the photoresist, utilizing an anti-reflective coating material, or changing the light source. Specifically, the present invention compensates for standing waves by exposing the photoresist with light from a light source at different phases. That is, in the present invention there is a change in light exposure from a single dose at one phase to a plurality of doses at different phases; therefore dispersing the effects of the standing wave at each of those phases which in turn eliminates the standing wave.

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

Abstract: A method and structure for an integrated circuit chip which includes forming a storage capacitor in a vertical opening in a horizontal substrate, forming a conductive strap laterally extending from the vertical opening and forming a transistor having a channel region extending along a vertical surface, the vertical surface lying outside of and being laterally displaced from the vertical opening, the transistor being electrically connected to the storage capacitor by an outdiffusion of the conductive strap.

Abstract: The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried-strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.

Abstract: A method of forming a semiconductor device, including forming a substrate with a memory array region and a logic device region, growing a thick gate dielectric over the substrate, forming a gate stack, including a first polysilicon layer, over the thick gate dielectric for the memory array region, forming a thin gate dielectric on the substrate over the logic device region, wherein layers of the gate stack in the memory array region protect the thick gate oxide during the forming of the thin gate dielectric, forming a second polysilicon layer for the gate stack in the logic device region, to produce a resulting structure, wherein a thickness of the second polysilicon layer is at least as thick as the gate stack in the memory array region, planarizing the structure using chemical mechanical polishing (CMP), and patterning the gate stacks in said memory array region and the logic device region.

Abstract: A method of enhancing the aluminum interconnect properties in very fine metalization patterns interconnecting integrated circuits that improves the texture and electromigration resistance of aluminum in thin films. Enhanced performance can be obtained by forming a smooth oxide layer in situ, or by surface conditioning a previously formed oxide layer in an appropriate manner to provide the requisite surface smoothness, then by refining the aluminum microstructure by hot deposition or ex-situ heat treatment.

Abstract: A method and structure for a dynamic random access memory chip includes memory element arrays having bitlines, a sense amplifier shared by the arrays. The sense amplifier includes multiplexors connected to the bitlines, an equalizer circuit connected to the multiplexors and a timer circuit connecting first bitlines to the sense amplifier a time period after second bitlines are sensed by the sense amplifier, wherein the time period is less than the active phase of the row cycle.

Abstract: A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.

Abstract: A method of forming a wiring pattern in a device comprises forming an array of grooves in a mask, forming first spacers adjacent vertical walls of the grooves, removing the mask, forming second spacers adjacent the first spacers, and filling areas between the first spacers and areas between the second spacers with a material to form the wiring pattern.

Abstract: An integrated circuit and a method of manufacturing an integrated circuit comprises forming an insulator over a substrate, forming a trench in the insulator and the substrate, undercutting the insulator to form a gate conductor opening between the substrate and the insulator adjacent the trench, and forming a gate oxide and gate conductor in the gate conductor opening.

Abstract: A nozzle apparatus and method of use for extruding a conductive paste through a stencil or screen onto a substrate are disclosed. The nozzle includes a body and a conformable insert for contacting the screen. The method comprises the steps of obtaining a substrate and a patterned screen, contacting the screen with a nozzle comprising a nozzle body and a conformable nozzle insert, and extruding a paste through the nozzle and screen onto the substrate. The apparatus and method are particularly useful for producing patterned lines from extruded pastes in the manufacture of microelectronic components.

Abstract: A shared row decoder and shared row decoding method are disclosed herein which provides separate timed selection signals to each of a first memory unit and a second memory unit. The shared row decoder includes an address input circuit responsive to the states of a plurality of address signals and which provides an enabling or disabling input. In addition, first and second selection circuits are provided which are responsive to enabled conditions of first and second block selection inputs, first and second timing signals, respectively and enabling input of the address input circuit to provide separate timed selection signals to the first and second memory units, respectively.

Abstract: A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends from the active device in a linear direction of the mesa. An embodiment is disclosed in which a plurality of active devices are formed in the mesa region and electrically connected thereby.

Abstract: A material deposition process is disclosed in which apertures of a contact mask used therein have a constricted opening terminating in a `knife edge` in a sidewall thereof near the top mask side, especially within the top 25% of the mask thickness above the substrate. A process is disclosed in which the mask, in addition, has apertures which have larger dimension lower openings on a bottom side of the mask contacting the substrate than constricted openings near the top side of the mask. Single solder bump and "bump on bump" over BLM (ball limiting metallurgy) processes are disclosed which utilize such contact mask to reduce the damage and detaching of such features during processing and subsequent handling.

Abstract: A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap. Also disclosed herein are methods of forming a semiconductor memory cell and of forming groups of semiconductor memory cells.

Abstract: A system is disclosed herein for stabilizing the current dissipation, voltage drop, and heating effects related to accessing blocks within first and second storage units of a double memory unit. The system includes a row selection unit located between the first and second storage units, which accesses storage locations of the first and second storage units according to first and second selection signals conducted from the outer extremities of the double memory unit to selected row locations. The blocks at corresponding distances from the outer extremities are numbered differently such that the sum of lengths of signal travel of the first and second selection signals to the numbered blocks remains relatively constant regardless of the block number which is selected for access.

Abstract: Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.

Abstract: A voltage control circuit for maintaining voltage levels on a pair of bitlines at a desirable above ground voltage is disclosed herein. In an exemplary embodiment, a semiconductor storage device includes a plurality of pairs of bitlines; a p-type field effect transistor multiplexer (PMUX) connecting each bitline of the pair to a sense amplifier; and a clamping circuit which prevents voltage levels on the bitlines from dwelling below a predetermined minimum voltage level. A method is also disclosed herein in which voltage levels on a pair of bitlines are maintained at a desirable above ground voltage level by connecting each bitline of a pair to a sense amplifier through a p-type field effect transistor multiplexer (PMUX); and clamping each bitline to prevent the voltage level thereon from dwelling below a predetermined minimum voltage level.

Abstract: A material deposition contact mask is disclosed in which apertures formed therein have a larger dimension in lower openings in a bottom side of the mask contacting the substrate than in constricted openings located near the top side of the mask. Apertures of the contact mask have knife edges located within the upper sidewalls thereof, e.g. within the top 25% of the mask thickness above the substrate. A mask is disclosed which, in addition, is thermally compensated to the substrate temperature at which the deposition is performed. Methods for fabricating the mask by differential etching are disclosed.

Abstract: In the manufacturing of 16 Mbit DRAM chips, the deep trench formation process in a silicon wafer by plasma etching is a very critical step when the etching gas includes 0.sub.2. As a result, the monitoring of the trench formation process and thus the etch end point determination is quite difficult. The disclosed monitoring method is based on zero order interferometry. The wafer is placed in a plasma etcher and a plasma is created. A large area of the wafer is illuminated through a view port by a radiation of a specified wavelength at a normal angle of incidence. The reflected light is collected then applied to a spectrometer to generate a primary signal S of the interferometric type. Next, this signal is applied in parallel to two filters. A low-pass filter produces a first secondary signal S1 that contains data related to the deposition rate and the redeposited layer thickness. A band-pass filter produces a second secondary signal S2 that contains data related to the trench etch rate and depth.