Abstract: A baffle has a slot, with the slot positioned between first and second adjacent components when the baffle is installed above the components. A pair of heatsinks are inserted into the slot, with at least one heatsink having a heat dissipating portion that remains above the slot after insertion into the slot. A spring is inserted into the slot between the pair of heatsinks.

Abstract: A system and method to intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. The first algorithm is a reduced load power saving algorithm. As the load decreases, duplicate instances of services can be gracefully suspended and the host processor cards hosting these instances can enter a power saving mode. The second algorithm is a priority-based power consumption reduction algorithm. If power consumption must be reduced, services having less of a contribution to revenue are suspended before components that having a higher contribution to revenue. The third algorithm is a minimal power-consuming redundant computing hardware algorithm that allows a “cold spare” host processor card to be pressed into service if another card fails.

Abstract: An assembly comprising a housing and a circuit board is designed to facilitate a simplified method of assembling the circuit board into the housing, along with a simplified method of coupling the signals on the circuit board to other circuits. The circuit board is guided into place by a pair of slots, with each slot located proximate an end of the housing. The housing includes a support member that has a deflection/retention feature that extends above a plane formed by the circuit board after the board has been assembled to the housing. The assembly is assembled by first partially inserting one end of the board into a slot and pressing the other end of the board toward another slot, with a curved guide deflecting the board downward and into the other slot. When both ends of the circuit board are inserted into the slots, the deflection/retention feature is in contact with the board and flexes the board upward.

Abstract: A networked system includes a fault tolerant storage system (FTSS) having an interconnection fabric that also carries network traffic. A plurality of servers are coupled to an FTSS via an FTSS interconnection fabric. As soon as a packet is received from a sending node, the packet is committed to reliable, persistent, and fault-tolerant storage media within the FTSS, and will not be lost. If the destination node is one of the servers coupled to the FTSS, the FTSS can send an acknowledgment to the sending node guaranteeing delivery to the destination node, even though the destination node has not yet received the packet. The packet is then transmitted to the receiving node, with the receiving node sending an acknowledgment to the FTSS when the packet has been received successfully.

Abstract: Embodiments of the present invention include a memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent. The memory controller includes at least one memory-controller agent, an incoming memory-transaction dispatch unit, and an outgoing memory-transaction completion unit. Each memory-controller agent has a memory-line memory controller and a memory-line coherency controller, along with a cache memory capable of caching the contents of a memory line along with coherency information for the memory line. Memory transactions are received from cacheable entities of a computer system at the incoming memory-transaction dispatch unit, and are then presented to one or more agents. If multiple memory-read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests.

Abstract: A method and apparatus pass messages between server and client applications using a fault tolerant storage system (FTSS). The interconnection fabric that couples the FTSS to the computer systems that host the client and server applications may also be used to carry messages. A networked system capable of hosting a distributed application includes a plurality of computer systems coupled to an FTSS via an FTSS interconnection fabric. The FTSS not only processes file-related I/O transactions, but also includes several message agents to facilitate message transfer in a reliable and fault tolerant manner. The message agents include a conversational communication agent, an event-based communication agent, a queue-based communication agent, a request/reply communication agent, and an unsolicited communication agent. The highly reliable and fault tolerant nature of the FTSS ensures that the FTSS can guarantee delivery of a message transmitted from a sending computer system to a destination computer system.

Abstract: Integer multiply operations using data stored in an integer register file are performed using multi-media primitive instructions that operate on smaller operands. The present invention performs a multiply operation on a 32-bit or 64-bit value by performing multiply operations on a series of smaller operands to form partial products, and adding the partial products together. Data manipulation instructions are used to reposition 16-bit segments of the 32-bit operands into positions that allow the multi-media parallel multiply instructions to compute partial products, and the partial products are then added together to form the result. In every embodiment, the present invention achieves better latencies than the prior art method of performing integer multiply operations provided by the IA-64 architecture.

Abstract: A method for prefetching instructions into cache memory using a prefetch instruction. The prefetch instruction contains a target field, a count field, a cache level field, a flush field, and a trace field. The target field specifies the address at which prefetching begins. The count field specifies the number of instructions to prefetch. The flush field indicates whether earlier prefetches should be discarded and whether in-progress prefetches should be aborted. The level field specifies the level of the cache into which the instructions should be prefetched. The trace field establishes a trace vector that can be used to determine whether the prefetching operation specified by the operation should be aborted. The prefetch instruction may be used in conjunction with a branch predict instruction to prefetch a branch of instructions that is not predicted.

Abstract: A multiprocessor computer system continues operation after the failure of a cooling device coupled to a central processing unit (CPU). In accordance with the present invention, an impending failure of a cooling device is detected, and all user and operating system processes are moved from the affected CPU coupled to the failing cooling device to one or more other CPUs. The system state is then altered so that interrupts are no longer received and processed by the affected CPU, and all memory caches associated with the affected CPU are flushed back to main memory to ensure cache coherency. At this point, the CPU is either powered-down, or placed in a low-power mode that allows the CPU to operate without the cooling device, while the processes that were removed from the suspended CPU continue executing on other CPUs.

Abstract: A method of assembling a circuit board into a housing to form an assembly is disclosed. The method includes inserting a first end of the circuit board into a first slot of the housing, flexing the circuit board over a deflection/retention feature, inserting a second end of the circuit board into a second slot of the housing, and pressing the circuit board into place until the circuit board clears the deflection/retention feature and snaps into place. The circuit board thereafter returns to a substantially flat state. Moreover, inserting a first end of the circuit board into a first slot of the housing and inserting a second end of the circuit board into a second slot of the housing each include simplifying initial alignment of the circuit board into the slot by first contacting a lower surface of the slot that extends farther from a front of the housing than an upper surface of the slot.

Abstract: A memory controller has separate memory controller agents that process memory transactions in parallel. A memory controller in accordance with the present invention includes a plurality of memory controller agents, which are coupled to each other via a series of busses, an incoming memory transaction dispatch unit, and an outgoing memory dispatch unit. Memory transactions are received from cacheable entities of a computer system at the incoming memory transaction dispatch unit, and are then presented to the plurality of agents. For each incoming transaction, one of the agents will accept the transaction. Each agent is responsible for ensuring coherency and fulfilling memory transactions for a single memory line. If multiple memory read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests.

Abstract: A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the present invention has R read ports and W write ports, and R is greater than W. In such a register file, each register will be accessed by W combined read/write word lines, a single direction line, and R-W read-only word lines. The direction line is asserted during a write operation, and is not asserted during a read operation, and also allows the storage elements comprising each register of the register file to be powered down or enter a high-impedance state during a write operation. During a read operation, the direction line remains deasserted and the storage elements remain powered up and active. For read ports sharing combined read/write word lines with write ports, the direction line is used as a multiplexer signal to enable a read operation at the read port represented by the combined read/write word line.

Abstract: An obstruction is removed from a computer system cooling fan by manipulating fan rotation. When a fan obstruction is detected, the fan is stopped. If the obstruction is caused by an object that was drawn toward the fan intake, such as a sheet of paper, this operation may clear the obstruction. The fan may also be reversed to attempt to blow the obstruction clear of the fan. Thereafter, the fan is returned to normal operation and is monitored to determine whether the obstruction was removed. If the fan is still obstructed, these steps can be repeated. If the attempts to clear the obstruction are unsuccessful, then the computer system operator or management software can be signaled.

Abstract: A cache memory replacement algorithm replaces cache lines based on the likelihood that cache lines will not be needed soon. A cache memory in accordance with the present invention includes a plurality of cache lines that are accessed associatively, with a count entry associated with each cache line storing a count value that defines a replacement class. The count entry is typically loaded with a count value when the cache line is accessed, with the count value indicating the likelihood that the contents of cache lines will be needed soon. In other words, data which is likely to be needed soon is assigned a higher replacement class, while data that is more speculative and less likely to be needed soon is assigned a lower replacement class. When the cache memory becomes full, the replacement algorithm selects for replacement those cache lines having the lowest replacement class.

Abstract: A voltage divider suppresses noise in a voltage divider output by filtering the voltages at the gate terminals of the transistors that comprise a voltage divider. In one embodiment of the present invention, a voltage divider includes a PFET transistor coupled between a voltage VDD and the voltage divider output, and an NFET transistor coupled between a voltage VSS and the voltage divider output, with a resistor-capacitor (RC) filter provided at each gate terminal of each of the transistors. In a second embodiment, the RC filter is fabricated using only transistors. In both embodiments, noise is filtered out at the gate terminal of the transistors, thereby eliminating noise in the resulting voltage divider output. Accordingly, a capacitor is not required between the voltage divider output and VSS, as in the prior art.

Abstract: A method and apparatus performs high bandwidth low latency programmed I/O (PIO) write operations by passing tokens. A computer system in accordance with the present invention includes a plurality of CPUs, with each CPU coupled to a CPU agent. Each CPU agents is coupled to an interconnection fabric, which in turn is coupled to an I/O agent and memory. The computer system may also have multiple I/O agents. Each I/O agent is coupled to an I/O card, and the computer system may have multiple I/O cards. The CPU agents and the I/O agents have token slots, and tokens circulate between the token slots. When a CPU seeks to write to an I/O card, the CPU forwards a PIO write request to the CPU agent. If the CPU agent does not have the token, the CPU agent sends the write data along with a request for the token to the I/O agent. If the token is currently owned by the I/O agent, it is sent to the CPU agent.

Abstract: A conductive clip is placed over a component mounted to a printed circuit board (PCB) to form a conductive path between terminals of the component. In one embodiment, a conductive clip is placed over a surface mount technology (SMT) component, with the clip having ends that include a flared portion and a sharp triangular retainment detent. In another embodiment, the clip has a shoe box shape and includes two sides having retainment detents that are disposed to engage an area between an edge of the component and the PCB. In yet another embodiment, the present invention is adapted for use with through hole mounted components having axial leads, with each end of the clip including a slot that engages a lead when the clip is pressed onto the component. The present invention allows a PCB to be designed to support multiple configurations without using DIP switches or headers/jumpers.

Abstract: A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time.

Abstract: A method and apparatus determines interleaving schemes in a computer system that supports multiple interleaving schemes. In one embodiment, a memory interleaving scheme lookup table is used to assign memory interleaving schemes based on the number of available bank bits. In another embodiment, the percentage of concurrent memory operations is increased by assigning memory interleaving schemes to bank bits based on the classification of bank bits. The present invention supports a memory organization that provides separate memory busses that support independent simultaneous memory transactions, and memory bus segments that allow memory read operations to be overlapped with memory write operations, with each memory bus segment capable of carrying single memory operation at any given time.

Abstract: A driver circuit compensates for skin effect losses in a transmission line by using a lower impedance when data switches at the maximum switching rate, and using a higher output impedance when data switches at less than the maximum switching rate. As is known in the art, skin-effect resistance causes the impedance of a transmission line to be higher for high-frequency components. A driver in accordance with the present invention compensates for this effect by lowering the output impedance of the driver when transmitting high-frequency components having alternating data values, and using a higher output impedance when transmitting low frequency components having consecutive data values.