Abstract: An address routing scheme supports a variety of memory sizes and interleaving schemes. In one embodiment, any address bit provided by the processor can be routed to any bank, row, or column bit, and can be used to generate any rank bit. This embodiment supports any type of interleaving scheme and memory modules constructed from a wide variety of DRAM chips. In another embodiment, a reduced routing function is used to generate rank bits and route address bits to subsets of bank, row, or column bits such that no route function encoding requires more than 3 bits. The second embodiment supports multi-cache line interleaving, cache effect interleaving, and DRAM page interleaving. Multi-cache line causes cache lines contained in small contiguous blocks to be contained in one DRAM page, while contiguous small contiguous blocks are stored on separate DRAM pages.

Abstract: A computer apparatus which detects a store or load operation into or from a shared memory page by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store into the shared memory page is performed until all prior store operations into the shared memory page are complete. Also, load operations are ordered such that load operations from the shared memory page are performed in program order. This ordering is achieved by maintaining a process bit and a memory attribute bit associated with a shared memory page. When both bits are true, all load or store operations referencing the shared memory page are ordered.

Abstract: A configuration agent allows a network node seeking to be automatically configured with an IP address and a default gateway address to be configured as its own gateway. In first and second embodiments of the present invention, the configuration agent resides on a network device (such as a switch or bridge) that is coupled to two network segments, with one network segments including a node to be configured and another network segment including a server capable of automatically providing configuration parameters. In the first embodiment, the configuration agent acts as a snoopy agent. Messages from the configuration server to the node to be configured are "snooped" to discover messages containing an IP address and a default gateway address. Such messages are altered to copy the IP addresses offered to the nodes seeking configuration to the default gateway addresses, and the messages are sent on their way, thereby causing the node seeking to be configured to be its own default gateway.

Abstract: A main memory indexing scheme optimizes consecutive page hits in computer systems having a main memory system and a cache memory. In accordance with the present invention, one or more bank select bits required by the main memory system are formed from one or more of the address bits that are used by the cache memory as the tag field. Preferably, the lower-order bits of the tag field are used. To increase the page hit rate even further, additional bank select bits are formed from the address bits immediately above the bits used to access columns. In one embodiment of the present invention, address bits are simply mapped to bank bits using a one-to-one correspondence. In another embodiment, address bits from the tag field and address bits immediately above the column bits are combined using a function such as an exclusive-OR operation or an addition operation, with the result of the function provided to the bank select bits.

Abstract: A STREAMS-based protocol stack is adapted to encrypt and decrypt data flowing through the stack. In a first embodiment, a STREAMS-based module is added to a protocol stack to encrypt and decrypt data flowing through the stack. In a second embodiment, a STREAMS-based encryption multiplexor routes data to and from an encryptor. In a third embodiment, dynamic function registration is used to register cryptographic functions at a stream head. In a fourth embodiment, STREAM-based modules are modified, either by dynamic function replacement or conventional means known in the art, to redirect data flowing between protocol stack layers to an encryptor. Hardware-based and software-based encryptor configurations are disclosed for all embodiments, as well as various methods of identifying cryptographic characteristics, such as cryptographic algorithms, public and private encryption keys, bindings to applications and IP addresses, and the like.

Abstract: A composite thermal interface pad is comprised of a template portion formed from a material such as thermal gap pad material or thermal tape, in which cavities have been formed and filled with a pliable non-resilient material, such as thermal grease or thermal putty. The spacing and size of the cavities may be tailored to achieve desired elastic properties and stress distributions, as well as optimize the thermal characteristics of the thermal interface with respect to heat distribution patterns of electronic components being cooled. The composite thermal interface pad may also be used to provide EMI shielding along the gap formed between the electronic component and the adjacent cooling structure by filling closely adjacent cavities with electrically conductive non-resilient material.

Abstract: An electrostatic discharge (ESD) damage prevention device is comprised of a spark gap coupled in series with a high-impedance network, with a first node of the series combination of the spark gap and high-impedance network coupled to a conductive location that may be subject to an electrostatic discharge and the second node coupled to a conductor capable of conducting away charge delivered by an ESD event. The spark gap defines the level of electrical isolation and the high-impedance network controls dissipation of charge delivered by an ESD event.

Abstract: A memory controller and at least one memory module exchange data at high transfer rates by minimizing clock skew. When writing data to the memory module, the memory controller generates a clock signal that travels along a first clock line segment. The data bus carries the write data, and the electrical characteristics of the data bus and first clock line segment are matched such that incident wavefronts of the data bus and clock signal arrive at the memory module in fixed relation to one another. When reading data, the first clock line segment is looped back from the memory module to the memory controller along a second clock line segment, with a copy of the clock signal provided on the second clock line segment. The data bus carries the read data, and the electrical characteristics of the data bus and the first clock line segment are matched such that incident wavefronts of the data bus and clock signal arrive at the memory controller in fixed relationship to one another.

Abstract: A method and apparatus in accordance with the present invention uses the unused bits of a data packet to transmit additional information by piggy-backing "secondary" code words into a data packet containing a "primary" code word. A secondary code word may be piggy-backed into a data packet containing a primary code word when the primary code word and any secondary code words already stored in the data packet leave sufficient unused space in the data packet to store an additional secondary code word, and the route traveled by the data packet as the packet is routed to the network node addressed by the primary code passes through (or ends at) the network node addressed by the secondary code word, or passes through (or ends at) a network node that can relay the secondary code word to the network node addressed by the secondary code word. In a first embodiment, an ECC is generated for the primary code word using a predefined bit pattern (such as all 0's) for any unused bit positions in the data packet.

Abstract: Branch predictions are adjusted by interrupting a central processing unit and observing a pending branch instruction. An interrupt is generated using a counter, timer, or software-based interrupt. The interrupt causes a prediction adjustment routine to execute, which in turn determines whether a pending branch instruction will branch. The actual branch behavior of the branch instruction is compared to the predicted branch behavior of the branch instruction, and the prediction is adjusted accordingly based on the accuracy of the prediction and previous branch behavior. After the prediction has been adjusted (if necessary), execution returns to the program that contains the branch instruction that was evaluated.

Abstract: An N-phase power converter uses a ring oscillator to generate a series of switching signals having substantially equally distributed phase relationships with respect to one another. The ring oscillator is formed from an alternating string of inverters and RC networks with the voltage over each capacitor of each RC network provided to a phase comparator. The phase comparators shape a saw-tooth waveform present over each capacitor into a pulse-width-modulated switching signal that drive switches which alternately charge and discharge inductors. One terminal of each inductor is coupled to common node at which the converter output voltage is provided. A feedback unit generates a feedback signal is used to vary the pulse width of the switching signals.

Abstract: A highly manufacturable low cost DC-to-DC power converter uses a control circuit constructed from a '555 type timer IC and a precision voltage reference. The output of the '555 timer is used to drive a MOSFET transistor that alternately energizes and de-energizes a primary winding of a transformer, thereby energizing secondary windings of the transformer. The voltage at the secondary windings is rectified and filtered to form the regulated output supply voltages. A feedback control signal is generated based on a difference between a reference voltage and the a regulated output supply voltage. Based on the feedback control signal, a control window is established within the '555 timer that determines the charging and discharging times of a capacitor. Since the charging and discharging times of the capacitor are exponential, changing the feedback control signal changes the control window, which in turn changes the charging time with respect to the discharging time.