Abstract: A mode control device for operation at a selected wavelength in cooperation with first and second waveguides, integrates first and second adjacent layers for passing electromagnetic energy from the first waveguide to the second waveguide through the layers in series. In a first embodiment, the first and second layers are composed of materials having a distinct indices of refraction and are spaced apart a distance other than one-quarter of said selected wavelength. In a second embodiment, the layers are disks having distinct circular diameters.

Abstract: A method and apparatus for resolving where to forward DNS (domain name service) requests for a user simultaneously logged into more than one service existing on a data communications network utilizes an active service list (ASL) to keep track of the services that the user is currently logged into. The active service list includes a list of services sorted in a particular order based on information about the service and sometimes the order in which the user logged into the services. Each service has a profile that defines, among other things, the IP Address space for the service and a Domain attribute. To determine the appropriate service and, therefore, the appropriate DNS server for a DNS request, the QName from the DNS request is compared to the configured Domain attribute(s) for each service in the order of the ASL. If a match is found, then the DNS request packet is modified to re-direct the DNS request to the DNS server configured for the matched service.

Abstract: A method for optimizing bytecode in the presence of try-catch blocks comprises generating an Intermediate Representation of the bytecode, scanning each basic block of the bytecode to identify try blocks, scanning each basic block of the bytecode to identify try-blocks, splitting each try-block into a first half and a second half at the first statement that can throw an exception, establishing an edge between the first half and the second half of each try-block, between the first half and the catch block, and between the catch block and the basic block subsequent to the second half of each try-block.

Abstract: A radio frequency identification system includes a transponder and a transponder reader. The transponder, responsive to an interrogation signal continuously transmitted by the transponder reader, generates a transponder signal modulated by an identification signal readable by the transponder reader. The identification signal includes a synchronization portion, a data portion, an output format identification portion, and an error detection portion. The output format identification portion is used by the reader to configure itself for communication with an attached controller. In another aspect of the invention, the transponder reader may be configured to read FSK as well as PSK encoded signals from the transponder.

Abstract: In order to load share non-configuration message traffic on more than one port of a non-root spanning tree protocol compliant switching node, upon receiving a spanning tree algorithm port-blocking message, the switching node assigns a port filter to each of its non-designated ports. The switching node then directs a spanning tree non-configuration message through a port that has a port filter which corresponds to the non-configuration message. The switching node may be implemented using any learning switch, or equivalent device, which complies with a spanning tree algorithm, has sufficient memory to store the port filters used, a means for applying the port filters to its non-designated ports, and a means for directing at least one spanning tree non-configuration message to a port having a port filter that corresponds to the non-configuration message. The switching node may be implemented on any spanning tree compliant network, such as a IEEE 802.

Abstract: A decimation filter includes a zero insertion filter having an input and an output, wherein the input forms an input of the decimation filter; a cascade of four comb filters having a first accumulator stage and a second stage having a first differentiator portion and second differentiator portion wherein the first stage has an input coupled to the output of the zero insertion filter and an output, the first differentiator portion has an input coupled to the output of the first stage and an output, and the second differentiator portion has an input coupled to the output of the first differentiator portion and an output, and a frequency shaping filter having an input and an output, wherein the input is coupled to the output of the second differentiator portion and the output forms an output of the decimation filter.

Abstract: A multi-phase power supply utilizes a current sensor including a sensor inductor winding connected in parallel with a filter inductor winding at the output of each phase for sensing the phase currents and balancing the current by adjusting the duty cycle of each phase through feedback control. In addition, in a multi-module power supply configuration, current between power supply modules is balanced through use of the same current sensor and current sharing technique. Each phase of the power supply includes at least one input power source and a current sensor. The sensor inductor winding and the filter inductor winding have the same number of turns and are wound about a magnetic core also present at each phase. A differential amplifier at each phase senses and amplifies any voltage difference between the outputs of the sensor inductor winding and the corresponding filter inductor winding.

Abstract: A method and apparatus for ensuring that information transfers from memory to a peripheral device are complete prior to the peripheral device executing instructions responsive to the content of the information is described. The method includes identifying lines of data to be written, determining a unique start code to be used for that data, and embedding that start code into that data. When the proper number of lines of data have arrived in peripheral device memory, the pending operation is executed.

Abstract: A method for providing network device status notification includes providing at least one auditory cue to indicate at least one device status. According to one aspect, distinct auditory cues are provided when a device begins looking for a federation, when a device has connected to federation and when a device has disconnected from a federation. A network device includes a network interface and an auditory cue unit coupled to the network interface to provide at least one auditory cue to indicate at least one activity status.

Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.

Abstract: A simplified algorithm for digital signal interpolation and a novel architecture to implement the algorithm in an integrated circuit (“IC”) with significant space constraints are presented. According to embodiments of the present invention, the interpolator is divided into two parts. The first part of the interpolator increases the sample rate by a factor of two and smoothes the signal using a half-band Infinite Impulse Response (“IIR”) filter. The second part of the interpolator increases the sample rate of the signal by a factor of thirty-two using a zero-order-hold (“ZOH”) circuit. In one embodiment, the half-band IIR filter is implemented using an all-pass lattice structure to minimize quantization effects. The lattice coefficients are chosen such that the structure can achieve all filter design requirements, yet is capable of being implemented with a small number of shifters and adders, and no multipliers.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provides a development tool that enables computer programmers to design and develop a data flow program for execution in a multiprocessor computer system. The tool displays an interface that enables the programmer to define a region divided into multiple blocks, wherein each block is formed of a set of values associated with a function, and to define sets of the blocks, each block in a set having a state reflected by a designated portion of the program that when executed transforms the values forming the block based on the function. The interface also records any dependencies among the blocks, each dependency indicating a relationship between two blocks and requiring the portion of the program associated with a first block of the relationship to be executed before the portion of the program associated with a second block of the relationship.

Abstract: A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent said grid insulator, a retention insulator disposed adjacent said grid electrode, and a floating gate electrode disposed adjacent said retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor.

Abstract: Network access requests, which may based on different access methods, are processed by using a protocol gateway that insulates the processing of the access requests from the specialized protocols required to obtain the necessary services required for the different access methods supported. In a first aspect of the present invention, this includes using a protocol handler that is responsive to the network protocol used by the access request. The protocol handler performs a set of steps necessary for responding to the access request. If the steps include procuring a state service, a state object is used to obtain the state service, insulating the protocol handler from having to communicate with a provider of the state service, such as a service component. Upon completion of the steps defined within the set of steps, the protocol handler denies or grants network access.

Abstract: The present invention manages a messaging network having messaging platforms interconnecting through a switched backbone such as the Internet. The master platform monitors each messaging platform on the messaging network and administers the addition, deletion, and updating of messaging platforms by modifying a master global routing table in the event the master platform encounters changes to the status of the messaging platforms. In the event that the master global routing table is updated, the global routing table held at each messaging platform is also updated, ensuring version consistency between said master global routing table and each of the global routing tables. This enables the master platform and each messaging platform to determine the operational status of another messaging platform. The present invention may also provide a cost tracking scheme when delivering messages between messaging platforms that are owned by different entities.

Abstract: An apparatus and method for virtual current sensing in a DC-DC switched mode power supply. In a fixed frequency implementation, when a switching phase begins, the phase node goes high when the high-side switching transistor is turned on. At this point, a first programmable current source begins charging a current sensing capacitor and the voltage across the capacitor simulates the rising slope of the voltage across a conventional current sensing resistor. Simultaneously, a ramp capacitor beginning at a reference voltage is charged by a second programmable current source. When the sum of the voltages across the two capacitors exceeds an error voltage, the phase node goes low when the drive signal to the transistor is turned off. At this point, a third programmable current source begins discharging the current sensing capacitor and the voltage across the capacitor simulates the falling slope of the current across the conventional resistor.

Abstract: The Internet appliance accesses an HTML page on a Web site containing configuration information for an Internet appliance, such as an Internet compatible telephone. Data from the HTML page are downloaded to the Internet appliance to modify its options or settings automatically upon accessing the HTML page, or as directed by the user. The data may be downloaded to a programmable memory in the Internet appliance and the stored data may be used to upgrade the Internet appliance. The upgrade HTML page may include information to alert the user when the new information is available regarding changes to options and settings of the Internet appliance. Alternatively, data from the Internet appliance are placed in an HTML page and the data are then uploaded to the Web site. Additional embodiments provide other functions that may be placed in an HTML page to effect some internal action in the Internet appliance, such as checking e-mail.

Abstract: A clock buffer circuit is disclosed. The clock buffer circuit is included in each sub-block of a clock distribution structure in an integrated circuit. Each clock buffer circuit comprises a plurality of driving inverters, and each clock buffer circuit presents an equal input load to the previous driver, regardless of the amount of load in the sub-block circuit. In each sub-block, the clock buffer circuit is connected to provide an output including the combined signals of a portion of the inverters. The portion is approximated by the load of the circuit in the sub-block divided by the load of the circuit in the sub-block having the greatest load of any sub-block. The outputs of inverters not connected to the load of the sub-block circuit are wired to power and ground terminals. Each driving inverter may comprise a pMOS FET paired with an nMOS FET. A method for designing such a clock buffer circuit is also disclosed.

Abstract: An ultrasound imaging method for forming an image of an object using received signals reflected from the object, received after transmitting an ultrasound pulse to the object.

Abstract: A data exchange system includes at least one transmitting agent, at least one receiving agent, and a plurality of data links each having a crossbar coupling respective transmitting agents and receiving agents. A stream of data packets including at least one Order Critical Flow of data packets having a critical order to be sent from the transmitting agent to the receiving agent is divided for transmission among the plurality of data links. Multiple Order Critical Flows between the transmitting agent and the receiving agent are possible and the packets within such Order Critical Flows can be intermixed for transmission (along with packets from other Non-Order Critical Flows).