Abstract: A switch gear with at least two gear stages is provided. At least one gear stage is configured as a switching stage, whereby at least one switching stage is formed by a coaxially nonrotatable sunwheel on a drive shaft, by at least one planet carrier carrying one planet wheel and by at least one ring gear meshing with the planet wheel on the inside, which is held fixed in its housing, and by a cam disk for the actuation of switching elements. The cam disk is provided with a female spline which exhibits approximately the identical pitch circle diameter as the female spline of the ring gear, whereby the female spline of the cam disk exhibits a number of teeth different from the female spline of the ring gear and whereby the cam disk, by means of the female spline, meshes with at least one planet wheel of the switching stage. The switch gear may be used, for example, as a limit switch of cranes.

Abstract: A package having a container having an inner surface, an outer surface, and a sidewall defining a cavity, with the container having an inner locking tab in the cavity defining a recess in the outer surface of the container, and with a stiffening material being placed in the recess to add strength to the locking tab.

Abstract: In a serial interface for a programmable hearing aid, no address is provided for the data transferred to or read from the hearing aid, rather, for each instruction, the number of data words being transferred pursuant to each instruction and the beginning word are known in the controlled device. In the serial interface, the data is clocked into and out of the hearing aid on a serial data pin by a serial clock. Because no addresses are sent along with the data to the controlled device, the amount of data transferred to the hearing aid is significantly reduced, and no circuitry is required to save the address.

Abstract: A step-down switched-mode power supply circuit includes a transformer having at least one primary winding and at least one secondary winding, a current sensing device for sensing a current through a primary winding of the transformer, a first switch and a second switch, a first comparator for determining if the current through the current sensing device exceeds a threshold, a voltage regulator coupled to the secondary winding to produce a regulated voltage, a second comparator for determining if the regulated voltage has drooped below an acceptable level, a counter coupled to the second comparator for generating a signal having a fixed number of switch cycles, and control circuitry for generating signals controlling the first switch and the second switch and responsive to the first comparator to enter a power saving mode disabling the signals, and to the second comparator to temporarily exit the power saving mode for a fixed number of cycles when the regulated voltage has drooped below an acceptable level.

Abstract: A system and method for remotely connecting client computers to a communication network such as the Internet by way of a server system handling a plurality of client computers and having the capability of dynamically providing network connections to the client computers, separately billing usage time and tracking usage and preferably updating access software on the client computers.

Abstract: According to a first aspect of the present invention, a method for linking bytecodes of an uninterrupted block of bytecodes in the formation of a data flow graph comprises the steps of scanning the uninterrupted block of bytecodes in a forward manner to identify the start of each of the bytecodes, scanning in a backward manner bytecodewise each of the bytecodes in the uninterrupted block of bytecodes, and generating a link in the data flow graph that links each of the bytecodes to all other of the bytecodes used by the each of the bytecodes.

Abstract: A current sensing device incorporated into the gate charge current path of the power transistor in a typical pulse-width modulated current mode switching power supply controller provides adaptive leading edge blanking of the current-sense waveform present in the feedback signal to prevent erroneous response in the feedback control circuitry and improve regulation of the power supply output voltage. A serial switch located within the current-sense feedback signal path is directly controlled by the current sensing device to open and close the signal path and generate a blanking interval which is optimally aligned to blank out or remove the leading edge spike in the current-sense waveform which corresponds to the gate charge current pulse that occurs during the turn-on transition of the power transistor.

Abstract: A multi-phase power supply utilizes a current sensor including a sensor inductor winding connected in parallel with a filter inductor winding at the output of each phase for sensing the phase currents and balancing the current by adjusting the duty cycle of each phase through feedback control. In addition, in a multi-module power supply configuration, current between power supply modules is balanced through use of the same current sensor and current sharing technique. Each phase of the power supply includes at least one input power source and a current sensor. The sensor inductor winding and the filter inductor winding have the same number of turns and are wound about a magnetic core also present at each phase. A differential amplifier at each phase senses and amplifies any voltage difference between the outputs of the sensor inductor winding and the corresponding filter inductor winding.

Abstract: The present invention evaluates the power dissipation of an electronic circuit. A power dissipation value is calculated for each transition or event generated during the electronic simulation of an electronic circuit design that corresponds to an actual electronic circuit. The present invention relies on data that includes an electronic circuit design description of the electronic circuit, such as a gate level netlist; a cell library having a power model corresponding to a cell instance; cell activity data such as net transitions; and the total effective load seen by each cell pin of the logic cell to be evaluated for power. The power model includes simple arcs (transition delay values, energy per arc values, cell input capacitances, and output slew rate values) and power evaluation data.

Abstract: A two-stage high power converter produces a highly regulated DC voltage from unregulated DC input. The first stage, having a plurality of interleaved buck regulators connected in parallel, converts unregulated DC voltage into regulated DC current. The second stage comprises a bridge for receiving the regulated current from the first stage, and converting it into AC voltage, which is in turn applied a step-up transformer. The secondary voltage of the transformer is rectified and filtered to produce low noise DC voltage. A method of converting unregulated DC voltage into regulated DC voltage comprises paralleling a plurality of interleaved buck regulators, where each of the buck regulators includes a switch. Each of the switches is controlled to operate at the same set frequency equal to two times the bridge operating frequency divided by the number of interleaved buck regulators. The combined current from interleaved buck regulators is fed to the bridge.

Abstract: A method and apparatus for reliable interrupt reception over a buffered bus utilizes a non-delayed non-posted write transaction to write data over the bus from a peripheral device to host memory. Because there is no buffering delay in a non-delayed non-posted write transaction, at the completion of the write cycle the peripheral knows that the write transaction is complete and then sends an interrupt request to the host processor requesting the host processor to service the interrupt and process the contents of the host memory.

Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

Abstract: A method and apparatus for storing a macroblock from a video data stream is disclosed. A macroblock is received, the macroblock having a plurality of blocks corresponding to a plurality of color space components and having a width defined by a plurality of pixels. According to a first aspect of the present invention, the macroblock is stored in a vertical strip format. According to a second aspect of the present invention, the contents of the plurality of blocks are interleaved. According to a third aspect of the present invention, the contents of the plurality of blocks are interleaved and the macroblock is then stored in a vertical strip format.

Abstract: A “pick-and-place” apparatus has a first pivoted lever driven in alternating directions of pivoting, the drive shaft of which is mounted centrally between a first location and a second location. In the end positions, which delimit the pivoting range, the pivoted lever always faces towards one location or the other location. A second pivoted lever is mounted at the end of the first lever and driven in the opposite direction thereto and with a predetermined gear ratio thereto, for example, resulting from a fixed toothed wheel by means of a toothed belt and a further toothed wheel. The chip gripper is connected to the end of the second lever. The gear ratio and the lengths of the two levers are matched to each other such that in both end positions, the two levers are in an extended position with respect to one another and the chip gripper is over the one location or the other location.