Patents Represented by Attorney, Agent or Law Firm David Denker
  • Patent number: 7115461
    Abstract: A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: October 3, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: John Mark Anthony, Scott R. Summerfelt, Robert M. Wallace, Glen D. Wilk
  • Patent number: 7030038
    Abstract: This invention pertains generally to forming thin oxides at low temperatures, and more particularly to forming uniformly thick, thin oxides. We disclose a low temperature method for forming a thin, uniform oxide 16 on a silicon surface 12. This method includes providing a partially completed integrated circuit on a semiconductor substrate 10 with a clean, hydrogen terminated or atomically flat, silicon surface 12; and stabilizing the substrate at a first temperature. The method further includes exposing the silicon surface to an atmosphere 14 including ozone, while maintaining the substrate 10 at the first temperature. In this method, the exposing step creates a uniformly thick, oxide film 16. This method is suitable for room temperature processing.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, Robert M. Wallace, Berinder P. S. Brar
  • Patent number: 6841439
    Abstract: A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: January 11, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: John Mark Anthony, Scott R. Summerfelt, Robert M. Wallace, Glen D. Wilk
  • Patent number: 6821554
    Abstract: This invention has enabled a new, simple nanoporous dielectric fabrication method. In general, this invention uses a polyol, such as glycerol, as a solvent. This new method allows both bulk and thin film aerogels to be made without supercritical drying, freeze drying, or a surface modification step before drying. Prior art aerogels have required at least one of these steps to prevent substantial pore collapse during drying. Thus, this invention allows production of nanoporous dielectrics at room temperature and atmospheric pressure, without a separate surface modification step. Although not required to prevent substantial densification, this new method does not exclude the use of supercritical drying or surface modification steps prior to drying. In general, this new method is compatible with most prior art aerogel techniques. Although this new method allows fabrication of aerogels without substantial pore collapse during drying, there may be some permanent shrinkage during aging and/or drying.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: November 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas M. Smith, William C. Ackerman, Richard A. Stoltz
  • Patent number: 6821835
    Abstract: A method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a conductive structure over the semiconductor substrate (step 106 of FIG. 1); and forming a layer of high-dielectric constant material between the conductive structure and the semiconductor substrate (step 102 of FIG. 1), the layer of high-dielectric constant material is formed by supplying a gaseous silicon source and a second gaseous material which is comprised of a material selected from the group consisting of: Hf, Zr, La, Y, Sc, Ce and any combination thereof.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: November 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Glen D. Wilk
  • Patent number: 6752962
    Abstract: A miniaturized integrated sensor (50) useful for indicating the presence of a sample analyte is disclosed. The sensor (50) has a platform (52) with an upper surface (53) and a detector (62), light source (60), waveguide (58), and reflective fixtures (60, 62) embedded in the platform (52). The light source (60) is preferably a light emitting diode and sits in a cup-shaped dimple (68) that directs light from the light source (60) toward one of the reflective fixtures (64) to uniformly distribute light across the waveguide (58). The waveguide (58) is coupled to an upper surface (53) of the sensor platform (52) and is coated with a thin film of indicator chemistry (70) which interacts with the sample analyte to produce optic signal changes that are measurable by the detector (62). A lead frame (51) in the platform (52) has pins (54, 55, 56) which provide the interface to the outside world.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: June 22, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Richard A. Carr, Jose L. Melendez, Kirk S. Laney
  • Patent number: 6730977
    Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: May 4, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, John Mark Anthony, Yi Wei, Robert M. Wallace
  • Patent number: 6700484
    Abstract: A network for detecting a substance includes at least two detectors that are capable of transmitting a signal, and a remote station capable of receiving the signal. The detectors are adapted to detect a substance and transmit data that indicates the presence of that substance to the remote receiving station.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: March 2, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Dwight Urban Bartholomew, Diane L. Arbuthnot
  • Patent number: 6653717
    Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critcal width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 25, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Manoj Kumar Jain, Michael Francis Chisholm
  • Patent number: 6645878
    Abstract: This invention has enabled a new, simple thin film nanoporous dielectric fabrication method. In general, this invention uses glycerol, or another low volatility compound, as a solvent. This new method allows thin film aerogels/low density xerogels to be made without supercritical drying, freeze drying, or a surface modification step before drying. Thus, this invention allows production of nanoporous dielectrics at room temperature and atmospheric pressure, without a separate surface modification step. Although this new method allows fabrication of aerogels without substantial pore collapse during drying, there may be some permanent shrinkage during aging and/or drying. This invention allows controlled porosity thin film nanoporous aerogels to be deposited, gelled, aged, and dried without atmospheric controls.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: November 11, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas M. Smith, Gregory P. Johnston, William C. Ackerman, Richard A. Stoltz, Alok Maskara, Teresa Ramos, Shin-Puu Jeng, Bruce E. Gnade
  • Patent number: 6613698
    Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: September 2, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, John Mark Anthony, Yi Wei, Robert M. Wallace
  • Patent number: 6593638
    Abstract: A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a high-dielectric-constant material layer (e.g. undoped BST 36) overlaying the conductive lightly donor doped perovskite layer. The conductive lightly donor doped perovskite layer provides a substantially chemically and structurally stable electrical connection to the high-dielectric-constant material layer. A lightly donor doped perovskite generally has much less resistance than undoped, acceptor doped, or heavily donor doped HDC materials. The amount of donor doping to make the material conductive (or resistive) is normally dependent on the process conditions (e.g. temperature, atmosphere, grain size, film thickness and composition). This resistivity may be further decreased if the perovskite is exposed to reducing conditions.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 15, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Howard R. Beratan, Bruce Gnade
  • Patent number: 6552388
    Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: April 22, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, Robert M. Wallace
  • Patent number: 6544875
    Abstract: A method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a conductive structure over the semiconductor substrate (step 106 of FIG. 1); and forming a layer of high-dielectric constant material between the conductive structure and the semiconductor substrate (step 102 of FIG. 1), the layer of high-dielectric constant material is formed by supplying a gaseous silicon source and a second gaseous material which is comprised of a material selected from the group consisting of: Hf, Zr, La, Y, Sc, Ce and any combination thereof.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: April 8, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Glen D. Wilk
  • Patent number: 6495907
    Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by e.g.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 17, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Manoj Kumar Jain, Michael Francis Chisholm
  • Patent number: 6487328
    Abstract: A grating (18) couples the waveguide region (36) of a semiconductor laser (11) to a dielectric waveguide (26). The waveguide region of the laser includes a mirror (15) at one end thereof and an absorber (19) at the other end thereof. The dielectric waveguide includes a reflector (24) therein to reflect a portion of the light coupled from the laser to the dielectric waveguide back into the laser waveguide region.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: November 26, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Jerome K. Butler, Lily Y. Pang, Gary A. Evans
  • Patent number: 6486520
    Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: November 26, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Yasutoshi Okuno, Scott R. Summerfelt
  • Patent number: 6419742
    Abstract: A method of forming lattice matched single crystal wide bandgap II-VI compound semiconductor films over a silicon substrate includes first cleaning (10) the silicon substrate. A passivation layer is formed (18), which may comprise arsenic, germanium, or CaF2, among others. The lattice matched layer is then grown (26) on the passivation layer.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: July 16, 2002
    Assignees: Texas Instruments Incorporated, Texas A&M University System
    Inventors: Wiley P. Kirk, Joe X. Zhou, Bruce E. Gnade, Chih-Chen Cho
  • Patent number: 6413437
    Abstract: The invention is a method of forming the art work for chemically etching that produces uniform through-etch and lateral-etch. The artwork that defines the pattern to be etched utilizes lines equal to the narrowest feature that is to be etched. Rather than etch away large areas, section are removed by etching by cutting them out of the material that is being etched. The artwork or pattern is designed with the same compensation factors throughout the entire pattern and the etch rate will be completely uniform for the entire pattern.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: July 2, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Robert M. Fritzsche
  • Patent number: 6399445
    Abstract: A method of fabricating a semiconductor MOS device and the device wherein there is initially provided a semiconductor substrate having a gate insulator layer thereon and intimate therewith. A region of one of a nitride or oxynitride is formed at the surface region of the layer remote from the substrate having sufficient nitride to act as a barrier against the migration of dopant therethrough to the substrate. A doped polysilicon gate or a metal gate is then formed over the region of a nitride or oxynitride. The amount of nitride in the insulator layer intimate and closely adjacent to the substrate is insufficient to materially alter the characteristics of the device being fabricated. The substrate is preferably silicon, the oxide and nitride are preferably those of silicon and the dopant preferably includes boron. The step of forming a region of one of a nitride or oxynitride includes the step of injecting neutral atomic nitrogen into the surface of the gate insulator layer surface remote from the substrate.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: June 4, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Sunil V. Hattangady, Srikanth Krishnan, Robert Kraft