Patents Represented by Attorney, Agent or Law Firm David G. Alexander
  • Patent number: 6245584
    Abstract: An adjustment error in a photolithographic stepping printer is detected by applying photoresist to a semiconductor wafer, and exposing the wafer to substantially identical light images in multiple locations using a stepping printer. The light images are defined by an optical reticle and include a plurality of lines or other features that are spaced from each other at approximately the resolution limit of the printer. Developer (16) is applied to the wafer to produce visible images corresponding to the light images. The visible images function as diffraction gratings which reflect light from the wafer. The visible images are inspected optoelectronically or manually. An adjustment error is determined to exist if the visible images appear substantially identical but are uneven or otherwise abnormal.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: June 12, 2001
    Assignee: Advanced Micro Devices
    Inventors: Vincent Marinaro, Eric Kent
  • Patent number: 6242924
    Abstract: The size of an internal void in an electrically conductive lead is measured by determining its electrical resistance at a plurality of A.C. frequencies, ranging from D.C. to a frequency on the order of 50 to 100 GHz at which the majority of current flows along the skin of the lead. The test data is compared with reference data for an electrically conductive reference lead having characteristics which are essentially similar to the test lead. The difference between the two sets of data increases with the size of an internal void in the test lead. The difference will be greatest at D.C. because the current will flow through substantially the entire cross-section of the lead and the cross-sectional area will be reduced by the internal void. The test data will approach the reference data as the frequency increases because the majority of the current will flow through the skin of the test lead and will be less affected by the internal void.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: June 5, 2001
    Assignee: Advanced Micro Devices
    Inventors: Tsui Ting Yiu, Yow Juang W. Liu, Young-Chang Joo, Sunil N. Shabde
  • Patent number: 6205059
    Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells, a power supply, and a controller which cooperates with the power supply to apply an erase pulse to the cells, and then erase verify a first byte of cells in each sector. If the first bytes in any sector has not passed erase verify, another erase pulse is applied to the cells of those sectors, and the first byte in each sector which did not pass erase verify the first time is erase verified again. This procedure is continued until the first byte in each sector has passed erase verify. Then, the sectors are processed in sequence to erase and erase verify every cell. First, an erase pulse is applied to all of the cells in the sector. Then, the first byte is erase verified. If the first byte passes erase verify (which it will because it did previously), the next byte is erase verified.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: March 20, 2001
    Assignee: Advanced Micro Devices
    Inventors: Ravi P. Gutala, Jonathan S. Su, Colin S. Bill
  • Patent number: 6190966
    Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon nitride etch stop layer which is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least 480° C. such that the etch stop layer has a very low concentration of hydrogen ions. The minimization of hydrogen ions, which constitute mobile positive charge carriers, in the etch stop layer, minimizes recombination of the hydrogen ions with electrons on the floating gate, and thereby maximizes data retention of the device.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: February 20, 2001
    Assignee: Vantis Corporation
    Inventors: Minh Van Ngo, Sunil Mehta
  • Patent number: 6185466
    Abstract: A distributed digital control system includes a plurality of control modules which are interconnected by a communication link. Each module includes a processor unit for running a control program, and a plurality of system databases which correspond to nodes in the system. Each module further includes a selector such as a Dual Inline Package (DIP) switch for inputting a node number. The program automatically selects the database corresponding to the input node number when the module is powered up. The system preferably utilizes the industry standard LonTalk® protocol, with each database including Standard Network Variable Types (SNVTs) and Standard Configuration Parameter Types (SCPTs) for the respective node. A default database is also stored in each module, which is automatically used by the program if the system databases are not found.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: February 6, 2001
    Assignee: Proteus Industries, Inc.
    Inventor: Mark R. Nicewonger
  • Patent number: 6170881
    Abstract: A textured pattern including raised lines, bumps, etc. is formed of ink on a front surface of a base sheet. A layer of reflective monochrome or holographic roll leafing is formed over the textured pattern such that the surface of the leafing follows that of the pattern to simulate embossing. An ink image is formed over the front surface of the sheet in an area not occupied by the roll leafing, and an additional ink image can be formed over at least part of the roll leafing. A protective transparent layer is formed over the leafing and ink image. The base sheet can be transparent, and a reflective layer can be formed on a rear surface of the sheet to reflect light back through the sheet and transparent portions of the ink image. Alternatively, the base sheet can be opaque, and an additional ink image can be formed on the rear surface of the sheet.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: January 9, 2001
    Assignee: Serigraph, Inc.
    Inventors: Joseph P. Salmon, Eugene M. Dukatz, Rashelle L. Ponchaud
  • Patent number: 6171793
    Abstract: A genetic sample is analyzed by providing a gene probe array including a plurality of genetic probes having different receptors. The sample is processed to include at least one fluorescently tagged ligand. The array is hybridized by exposing the probes to the processed sample such that ligands can bind to complementary receptors. Composite data having a data dynamic range is obtained from the array using an optical scanner which has a scanner dynamic range that is smaller than the data dynamic range. The scanner optically irradiates and scans the probes and detects fluorescent emissions at a first wavelength which is selected such that the scanner produces valid first data in a low intensity portion of the data dynamic range and is in saturation in at least part of a high intensity portion of the data dynamic range.
    Type: Grant
    Filed: April 19, 1999
    Date of Patent: January 9, 2001
    Assignee: Affymetrix, Inc.
    Inventors: Vincent E. Phillips, Huu Minh Tran, Thomas Ryder, Anthony J. Berno, Ghassan Ghandour
  • Patent number: 6128607
    Abstract: One or more machine code entities such as functions are created which represent solutions to a problem and are directly executable by a computer. The programs are created and altered by a program in a higher level language such as "C" which is not directly executable, but requires translation into executable machine code through compilation, interpretation, translation, etc. The entities are initially created as an integer array that can be altered by the program as data, and are executed by the program by recasting a pointer to the array as a function type. The entities are evaluated by executing them with training data as inputs, and calculating fitnesses based on a predetermined criterion. The entities are then altered based on their fitnesses using a machine learning algorithm by recasting the pointer to the array as a data (e.g. integer) type. This process is iteratively repeated until an end criterion is reached.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: October 3, 2000
    Inventors: Peter Nordin, Wolfgang Banzhaf
  • Patent number: 6034542
    Abstract: An on-chip bus structure for use in a modularized integrated circuit chip including an FPGA module(s). The bus is intended for memory mapped data transfers between circuit modules, for instance master, slave, master/slave, bus controller, and bus monitor type modules. Each circuit module is an on-chip function block including a bus interface and communicates by a predefined set of bus signals; at least one module is an FPGA (field programmable gate array). Each module acts as a bus master when it initiates data read or write operations, or may be addressed during a bus read/write operation and thereby acts as a bus slave. This bus and module structure allows implementation of a system on a single chip.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: March 7, 2000
    Assignee: Xilinx, Inc.
    Inventor: David J. Ridgeway
  • Patent number: 6026838
    Abstract: An apparatus detects an opening in a fluid flow passageway such as occurs when a resistance welding cap which is cooled by the fluid flow becomes accidently detached from a welding machine. Upon detection of an opening, an air-actuated pinch lever is activated to quickly pinch shut flexible fluid inlet and outlet hoses and thereby shut off the fluid flow. Inlet and outlet flow rate sensors provide periodic outputs to a digital computer which determines directions of inlet and outlet flow acceleration. If either the inlet or outlet acceleration changes direction, a baseline inlet or outlet flow rate is set equal to the corresponding current flow rate value to prevent erroneous opening detection due to normal flow fluctuations. If the inlet and outlet accelerations are in the same direction, the baseline values are similarly updated. If the inlet acceleration is positive and the outlet acceleration is negative, it indicates a probable opening.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: February 22, 2000
    Assignee: Proteus Industries, Inc.
    Inventors: Mark R. Nicewonger, Tommy K. Yiu
  • Patent number: 5956707
    Abstract: A system for obtaining target data from a conventional computer database in response to an input query which has at least one attribute includes a Type Abstraction Hierarchy (TAH) manager for providing a TAH structure including relaxation conditions for said at least one attribute. A control unit successively applies a database query which corresponds to the input query to and receives data from the database, with progressively relaxed conditions of the attribute(s) being provided by the TAH manager, until the target data in the form of a specified number of ranked answers which satisfy the attribute conditions is obtained. The attribute relaxation process can be controlled such as relaxation order, preference list, reject, etc. to obtain user and context specific answers. The system can produce approximate answers or answers to query with conceptual terms. The input query can including cooperative operators such as "APPROXIMATELY", "NEAR TO" or "SIMILAR TO" or conceptual terms (e.g.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: September 21, 1999
    Inventor: Wesley W. Chu
  • Patent number: 5950667
    Abstract: An apparatus detects an opening in a fluid flow passageway such as occurs when a resistance welding cap which is cooled by the fluid flow becomes accidently detached from a welding machine. Upon detection of an opening, an air-actuated pinch lever is activated to quickly pinch shut flexible fluid inlet and outlet hoses and thereby shut off the fluid flow. Inlet and outlet flow rate sensors provide periodic outputs to a digital computer which determines directions of inlet and outlet flow acceleration. If either the inlet or outlet acceleration changes direction, a baseline inlet or outlet flow rate is set equal to the corresponding current flow rate value to prevent erroneous opening detection due to normal flow fluctuations. If the inlet and outlet accelerations are in the same direction, the baseline values are similarly updated. If the inlet acceleration is positive and the outlet acceleration is negative, it indicates a probable opening.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: September 14, 1999
    Assignee: Proteus Industries, Inc.
    Inventors: Mark R. Nicewonger, John W. Clove
  • Patent number: 5949693
    Abstract: A formal drawing for a machine part includes datum features that are used to construct a Datum Reference Frame (DRF) for the part. A Feature Control Frame (FCF) containing a datum feature that is intended to eliminate roll about a fixed primary axis of the DRF includes a material location modifier which specifies whether the orientation or the location of the feature should be used to eliminate roll. The material location modifiers enable specification of Independent of Material Location (IML), at Basic Material Location (BML), at Maximum Material Location (MML) and at Least Material Location (LML), eliminate all ambiguity in the formal drawing, and enable a DRF to be constructed automatically using a computer. The material location modifiers further eliminate any possibility of misinterpretation of the formal drawing during all stages of manufacture and inspection of the part.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: September 7, 1999
    Inventor: William Tandler
  • Patent number: 5946674
    Abstract: One or more machine code entities such as functions are created which represent solutions to a problem and are directly executable by a computer. The programs are created and altered by a program in a higher level language such as "C" which is not directly executable, but requires translation into executable machine code through compilation, interpretation, translation, etc. The entities are initially created as an integer array that can be altered by the program as data, and are executed by the program by recasting a pointer to the array as a function type. The entities are evaluated by executing them with training data as inputs, and calculating fitnesses based on a predetermined criterion. The entities are then altered based on their fitnesses using a machine learning algorithm by recasting the pointer to the array as a data (e.g. integer) type. This process is iteratively repeated until an end criterion is reached.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: August 31, 1999
    Inventors: Peter Nordin, Wolfgang Banzhaf
  • Patent number: 5946214
    Abstract: A computer is used to estimate a fabrication yield for a semiconductor product under design which includes a plurality of integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme in the form of redundant rows and/or columns. A bitmap failure analysis of an existing semiconductor product including a plurality of integrated circuit dies having bitmap failure modes that are comparable to those of the product being designed is performed to obtain a number of failed caches. An observed repair rate is computed as a ratio of a number of the failed caches that can be repaired by the predetermined redundancy scheme to the number of failed caches. A model repair rate for the predetermined redundancy scheme which approximates the observed repair rate is computed using a multiple Poisson model including computed average numbers .lambda. of failures for the failure modes respectively. The numbers .lambda.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: August 31, 1999
    Assignee: Advanced Micro Devices
    Inventors: William D. Heavlin, Richard C. Kittler, Ping Wen
  • Patent number: 5915288
    Abstract: A plurality of pre-recorded, generated or other sound tracks (e.g. voice, karaoke) are selectable and de-selectable by a user for synchronously mixing with a main song track and all other sound tracks that are playing. The sound tracks are matched and synchronized to the song track. A visual display depicts icons which represent the sound tracks, and indicate which sound tracks are selected and de-selected. The user creates an individual musical performance by interactively selecting and de-selecting one or more sound tracks using a joystick or keyboard on a real-time basis with instantaneous visual and audible feedback. Depending on the musical content of each sound track, various operational modes ensure that whenever a track is selected, the result is always immediate, musically synchronized and aesthetically pleasing.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: June 22, 1999
    Assignee: Interactive Music Corp.
    Inventor: Joshua Gabriel
  • Patent number: 5907705
    Abstract: Change control in a software release stream is managed by a computer implemented Request To Integrate (RTI) system, including at least one user unit having an input unit and a display. A server unit which is connected to the user unit(s) creates and stores RTI files representing requests to integrate changes into the software release stream, and enables a selected RTI file to be displayed on the display unit under control of the input unit. The server unit includes a database in which the RTI files are stored under the Source Code Control System (SCCS), and a search engine for searching the database and displaying selected RTI files and their histories. The RTI files are in World Wide Web (WWW) HyperText Markup Language (HTML) text format, and are accessible through a WWW browser in the user unit(s) and a cooperating WWW server in the server unit. The server unit stores and executes a program including a WWW home page, and developer, evaluator and gatekeeper pages which are accessible through the home page.
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: May 25, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Bruce Carter
  • Patent number: 5901090
    Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the power source to apply at least one erase pulse to the cells. Then, at least one overerase correction or "soft programming" pulse is applied to the cells during which the source, drain and control gate voltages of the cells are such that the threshold voltages of overerased cells will be increased, but least erased cells will not be disturbed. The overerase correction pulses thereby tighten the threshold voltage distribution. A source to substrate bias voltage is applied for the duration of the overerase correction pulses which reduces the background leakage of the cells to a level at which the overerase correction operation can be effectively performed, even in applications with low supply voltages.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: May 4, 1999
    Assignee: Advanced Micro Devices
    Inventors: Sameer S. Haddad, Wing H. Leung, John Chen, Ravi S. Sunkavalli, Ravi P. Gutala, Jonathan S. Su, Colin S. Bill, Vei-Han Chen
  • Patent number: 5875130
    Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: February 23, 1999
    Assignee: Advanced Micro Devices
    Inventors: Sameer S. Haddad, Wing H. Leung, John Chen, Ravi S. Sunkavalli, Ravi P. Gutala, Jonathan S. Su, Vei-Han Chan, Colin S. Bill
  • Patent number: 5841947
    Abstract: One or more machine code entities such as functions are created which represent solutions to a problem and are directly executable by a computer. The programs are created and altered by a program in a higher level language such as "C" which is not directly executable, but requires translation into executable machine code through compilation, interpretation, translation, etc. The entities are initially created as an integer array that can be altered by the program as data, and are executed by the program by recasting a pointer to the array as a function type. The entities are evaluated by executing them with training data as inputs, and calculating fitnesses based on a predetermined criterion. The entities are then altered based on their fitnesses using a machine learning algorithm by recasting the pointer to the array as a data (e.g. integer) type. This process is iteratively repeated until an end criterion is reached.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: November 24, 1998
    Inventor: Peter Nordin