Abstract: Non-impact offset printing apparatus providing repeatable top-to-bottom registration of printed matter transferred to cut sheet paper fed in the "portrait" direction by means of a timer-interposer mechanism which contacts the leading edge of each incoming sheet and times the entry of the sheet into the transfer point adjacent to the rim of the offset non-impact rotary printing apparatus effectively creating positive and accurate registration of all four margins of printed matter on each page.

Abstract: A data processing system having a plurality of processors and a plurality of dedicated and shared memory modules. Each processor includes a cache for speeding up data transfers between the processor and its dedicated memory and also between the processor and one or more shared memories. The integrity of the data in each cache with respect to the shared memory modules is maintained by providing each shared memory with a cache monitoring and control capability which monitors processor reading and writing requests and, in response to this monitoring, maintains an accurate, updatable record of the data addresses in each cache while also providing for invalidating data in a cache when it is no longer valid.

Abstract: This invention is directed to the making of an electrode assembly which comprises providing anode electrodes on one surface of a photosensitive glass plate, providing cathode electrodes on the opposite surface of said glass plate oriented transversely to said anode electrodes, and dissolving away the plate material in alignment with said anode electrodes forming slots extending between the surfaces of said plate, thereby placing said anode and cathode electrodes in operative relation with each other.

Abstract: An apparatus for automatic bursting of perforated continuous forms is disclosed. The apparatus comprises first and second feeder means which may comprise two pairs of rotating rollers with tensioning means being provided by rotating the roller pairs at a slight speed differential. The apparatus also includes releasing means for intermittently releasing the feeding action of the first feeder means or roller pair. The releasing means may be provided by a flat area on the surface of one of the low speed rollers for releasing the nip in the low speed rollers to allow the forms to slip and uncrinkle. The apparatus also includes first and second forms separation means which cooperate with perforations in the forms to separate the forms, the first separation means acting when no immediately preceding forms slippage has occurred and the second separation means acting when immediately preceding forms slippage has occurred.

Abstract: A preformatted optical recording disk for use in an optical data storage system in which a laser beam of predetermined frequency is focused on the disk. The disk comprises a substrate having reflective, dielectric and absorbing layers deposited in a manner so as to establish an anti-reflection condition for an incident laser beam. The disk is preformatted by recording optical holes in the absorbing layer so as to form one or more tracks wherein each track includes a plurality of headers positioned at predetermined locations along the track. Each header comprises a plurality of optical holes constructed and arranged so as to constitute predetermined embedded timing, track following and focusing data on the disk for use by an optical data storage system.

Abstract: A microprogrammed data processing system is provided in which each high level instruction is performed by one or more tasks, each task being in turn performed by executing one or more task microinstructions in a microprogrammed manner. Dynamic resource allocation and task synchronization are additionally provided along with a three-stage pipelined architecture so as to provide both multiprogramming and multiprocessing on a microinstruction level.

Abstract: The invention is a defect tolerant memory for a computer system. The defect tolerant memory has a main memory, a redundant memory and a mask memory. The redundant memory receives and stores data redundant to that addressed to defective cells in the main memory. The redundant memory has multiple memory levels and uses a randomness technique to store redundant data for all chips of the main memory. The mask memory stores the location of each defect of main memory and indicates when a defective word is addressed in main memory. The mask memory is made up of multiple bit mask memories each cooperating with one of the redundant memory levels. Each bit-mask memory has multiple sub-memory units which use a randomness technique to store the addresses of defects in main memory.

Abstract: The invention relates to photo-optical detection by coded aperture in which photo-optical keyboard apparatus includes a pattern arrangement of keys in rows and columns wherein each row is provided with a light source or generator optically couplable to a light receiver or receptor and including individual key stems each of which is provided with a light transfer attenuating, limiting or constricting element each element being arranged to pass or restrict a percentage of the light from source to receptor, key to key, by column to row effective to indicate the precise key position or location as a result of the actuation or depression of any key in the pattern arrangement. By electrically multiplexing the light signals a minimum circuit complex is required.

Abstract: A servo system uses a position demand signal to drive a servo to position a transducer head over a specific track on a disc. The position demand signal is referenced to a tribit servo track on the disc. A tribit servo track demodulator circuit, similar to that taught by Mueller in U.S. Pat. No. 3,691,543, is used to compute a correction signal to be applied to the position demand signals used in the servo system. In the demodulator circuit (similar to the Mueller reference), first and second position indicating signals from the tribit servo track are processed on two parallel detection paths to compute an error signal.

Abstract: Register selection apparatus which includes a plurality of specially mapped programmable memories each addressed by a respective portion of an updatable allocation register which indicates the free and assigned states of a plurality of registers. The resulting memory words read out from the memories are applied to a plurality of multiplexers for identifying a particular predetermined group of registers as being available for assignment. The memory words also provide signals for use in determining whether a sufficient number of free registers are currently available for assignment.

Abstract: A very fast BCD-to-binary converter useful for addressing a digital memory. The converter includes a logical level comprised of at least three specially chosen AND-OR-INVERT integrated circuit gates, having at least five inputs, for producing binary output signals representing bits of the converted binary number.

Abstract: Apparatus which detects and corrects both transient and single bit memory read errors while selectively logging only solid (that is, hardware-related) single bit memory read errors. Each of a plurality of memory modules directly transmits uncorrected memory data to a processor memory control while also providing for automatic local restoring of corrected data back into the memory address which produced the single bit error. The processor memory control provides its own error detection and correction employing syndrome generating and decoding circuitry which detects both multiple and single bit errors. Multiple bit errors are not corrected, but merely brought to the attention of the processor. Single bit errors are corrected, but only those which are found to most likely be solid errors are logged. A solid single bit error is recognized by detecting when two single bit errors having the same memory address occur consecutively.

Abstract: A positioning servomechanism, which is liable to damage, or positions other equipment which is liable to damage if extremeties in its positioning locus are encountered at speed, is protected against uncontrolled and catastrophic acceleration towards these extremeties by the provision of apparatus which shuts off power to the servomechanism in the event of its drive output exceeding a predetermined limit, indicative of saturation, for more than a predetermined time period, power being restored by the application of an external signal.

Abstract: The disclosure is of a system for operating a dot matrix display panel including elongated anodes and cathodes oriented transversely to each other to define columns of D.C. scanning cells. An array of quasi A.C. display cells is provided spaced from the D.C. scan cells by an apertured electrode plate. Operation of the D.C. scan cells to transfer glow from a scan cell to an associated display cell is achieved by momentarily turning off the scan cell by the application of a negative pulse to its anode. To prevent the coupling of this pulse to adjacent anodes and spurious operation of adjacent scan cells and display cells, a counter-balancing positive pulse is applied to all anodes. The preferred coupling circuitry includes coupling capacitors which can pass both of these positive and negative pulses.

Abstract: Automatically updatable error logging means incorporated in a multi-phase, bit addressable, variable field memory system. The memory system is partitioned into a plurality of individually addressable memory stacks and employs time-shared accessing of the memory stacks along with time-shared error detection and correction which is used with the error logging means to provide for automatic logging of detected errors during memory accesses on a priority basis.

Abstract: Apparatus which detects and corrects both transient and single bit memory read errors while selectively logging only solid (that is, hardware-related) single bit memory read errors. Each of a plurality of memory modules directly transmits uncorrected memory data to a processor memory control while also providing for automatic local restoring of corrected data back into the memory address which produced the single bit error. The processor memory control provides its own error detection and correction which detects both multiple and single bit errors. Multiple bit errors are not corrected, but are merely brought to the attention of the processor. Single bit errors are corrected but only those which are found to most likely be solid errors are logged. A solid single bit error is recognized by detecting when two single bit errors having the same memory address occur consecutively.

Abstract: The tape transport mechanism, in a tape drive for retrievable informational data storage, is provided with a cross-coupled tape speed control servomechanism, achieving controlled bidirectional movement and stopping of tape, without switching, and requiring only one polarity of power source for the motive elements.

Abstract: The disclosure is of a vacuum fixture comprising a pair of plates having a vacuum space between them and with a plurality of suction holes in one plate providing communication between said vacuum space and the outside world. A handle is secured to the plates, and the handle includes tubing coupled to the vacuum space and a control valve for applying suction force to the vacuum space and to a sheet or body supported on the one plate and held down thereon by the suction force.

Abstract: An improved copy-proof document is disclosed having a cancellation phrase with an alternating dot pattern which enhances both the detail rendition and protection of such documents. The method of making such a document by preprinting the cancellation phrase in a single tone pattern of alternating dot sizes is also disclosed.

Abstract: The disclosure is of a display panel which contains a plate having two arrays of accurately dimensioned slots in which electrodes are disposed. The first array of shallow slots are formed in the plate by an etching process, and the second array of deeper slots are formed in the plate by an etching or grinding process. Electrodes are seated in the slots to form an array of rows and columns of cells.